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International Conference on Parallel Processing and Applied Mathematics

PPAM 2013: Parallel Processing and Applied Mathematics pp 613–621Cite as

Efficient Execution of Erasure Codes on AMD APU Architecture

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Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 8384))

Abstract

Erasure codes such as Reed-Solomon codes can improve the availability of distributed storage in comparison with replication systems. In previous studies we investigated implementation of these codes on multi/many-core architectures, such as Cell/B.E. and GPUs. In particular, it was shown that bandwidth of PCIe bus is a bottleneck for the implementation on GPUs.

In this paper, we focus on investigation how to map systematically the Reed-Solomon erasure codes onto the AMD Accelerated Processing Unit (APU), a new heterogeneous multi/many-core architecture. This architecture combines CPU and GPU in a single chip, eliminating costly transfers between them through the PCI bus. Moreover, APU processors combine some features of Cell/B.E. processors and many-core GPUs, allowing for both vectorization and SIMT processing simultaneously.

Based on the previous works, the method for the systematic mapping of computation kernels of Reed-Solomon and Cauchy Reed-Solomon algorithms onto the AMD APU architecture is proposed. This method takes into account properties of the architecture on all the levels of its parallel processing hierarchy.

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Authors and Affiliations

  1. Institute of Computer and Information Sciences, Czestochowa University of Technology, Dabrowskiego 73, 42-201, Czestochowa, Poland

    Roman Wyrzykowski, Marcin Woźniak & Lukasz Kuczyński

Authors
  1. Roman Wyrzykowski
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  2. Marcin Woźniak
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  3. Lukasz Kuczyński
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Corresponding author

Correspondence to Marcin Woźniak .

Editor information

Editors and Affiliations

  1. Institute of Computer and Information Science, Czestochowa University of Technology, Czestochowa, Poland

    Roman Wyrzykowski

  2. University of Tennessee, Department of Computer Science, Knoxville, Tennessee, USA

    Jack Dongarra

  3. Institute of Computer and Information Science, Czestochowa University of Technology, Czestochowa, Poland

    Konrad Karczewski

  4. Technical University of Denmark Informatics and Mathematical Modelling, Kongens Lyngby, Denmark

    Jerzy Waśniewski

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Wyrzykowski, R., Woźniak, M., Kuczyński, L. (2014). Efficient Execution of Erasure Codes on AMD APU Architecture. In: Wyrzykowski, R., Dongarra, J., Karczewski, K., Waśniewski, J. (eds) Parallel Processing and Applied Mathematics. PPAM 2013. Lecture Notes in Computer Science(), vol 8384. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-55224-3_57

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  • DOI: https://doi.org/10.1007/978-3-642-55224-3_57

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-55223-6

  • Online ISBN: 978-3-642-55224-3

  • eBook Packages: Computer ScienceComputer Science (R0)

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