Zusammenfassung
In diesem Artikel wird ein System zur Generierung maschinensensitiver Postpassoptimierer und -analysatoren auf Assemblerebene vorgestellt, das speziell im Hinblick auf hochleistungsfähige Optimierungen für irreguläre Architekturen entworfen wurde. Für jede Zielarchitektur wird ein phasengekoppelter Codeoptimierer zur Durchführung integrierter globaler Instruktionsanordnung, Registerzuweisung und Ressourcenallokation auf der Basis ganzzahliger linearer Programmierung (ILP) generiert. Alle relevanten Informationen über die Zielarchitektur werden in der Maschinenbeschreibungssprache Tdl spezifiziert. Die ganzzahligen linearen Programme können entweder exakt oder durch Einsatz ILP-basierter Approximationen gelöst werden, wodurch die Berechnung hochqualitativer Lösungen in akzeptabler Zeit ermöglicht wird. Die Leistungsfähigkeit dieses Ansatzes wird durch eine Reihe praktischer Experimente belegt.
Mitglied des Graduiertenkollegs „Effizienz und Komplexität von Algorithmen und Rechenanlagen“ (gefördert durch die DFG).
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
Literatur
Analog Devices. ADSP-2106x SHARC User’s Manual, 1995.
S. Arya. An Optimal Instruction Scheduling Model for a Class of Vector Processors. IEEE Transactions on Computers, 1985.
S. Bashford and R. Leupers. Phase-Coupled Mapping of Data Flow Graphs to Irregular Data Paths. Design Automation for Embedded Systems, pages 1–50, 1999.
F. Bodin, Z. Chamski, E. Rohou, and A. Seznec. Functional Specification of SALTO: A Retargetable System for Assembly Language Transformation and Optimization, rev. 1.00 beta. INRIA, 1997.
E. Farquhar and E. Hadad. TriCore Architecture Manual. Siemens AG, 1997.
A. Faut h, J. Van Praet, and M. Freericks. Describing Instruction Set Processors Using nML. In Proceedings of the EDAC, pages 503–507. IEEE, 1995.
C. Ferdinand. Cache Behavior Prediction for Real-Time Systems. PhD thesis, Saarland University, 1997.
C. Ferdinand, D. Kästner, M. Langenbach, F. Martin, M. Schmidt, J. Schneider, J. Theiling, S. Thesing, and R. Wilhelm. Run-Time Guarantees for Real-Time Systems — The USES Approach. Proceedings of the ATPS, 1999.
J.A. Fisher. Trace Scheduling: A Technique for Global Microcode Compaction. IEEE Transactions on Computers, pages 478–490, 1981.
C.H. Gebotys and M.I. Elmasry. Global Optimization Approach for Architectural Synthesis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pages 1266–1278, 1993.
R. Govindarajan, Erik R. Altman, and Guang R. Gao. A Framework for Resource Constrained Rate Optimal Software Pipelining. IEEE Transactions on Parallel and Distributed Systems, (11), 1996.
G. Hadjiyiannis. ISDL: Instruction Set Description Language Version 1.0. Technical report, MIT RLE, 1998.
A. Halambi, P. Grun, V. Ganesh, Khare A., N. Dutt, and A. Nicolau. EXPRESSION: A Language for Architecture Exploration through Compiler/Simulator Re-targetability. DATE, 1999.
S. Hanono and S. Devadas. Instruction Scheduling, Resource Allocation, and Scheduling in the AVIV Retargetable Code Generator. In Proceedings of the D AC. ACM, 1998.
ILOG S.A. ILOG CPLEX 6.5 User’s Manual, 1999.
D. Kästner. Retargetable Code Optimization by Integer Linear Programming. PhD thesis, Saarland University, 2000. To appear.
D. Kästner. TDL: A Hardware and Assembly Description Language. Technical report, Transferbereich 14, Saarland University, 2000.
D. Kästner and M. Langenbach. Integer Linear Programming vs. Graph-Based Methods in Code Generation. Technical report, Saarland University, 1998.
D. Kästner and M. Langenbach. Code Optimization by Integer Linear Programming. In Proceedings of the CC, pages 122–136, 1999.
D. Kästner and S. Thesing. Cache Sensitive Pre-Runtime Scheduling. In Proceedings of the LCTES Workshop, 1998.
Daniel Kästner. Instruktionsanordnung und Registerallokation auf der Basis ganzzahliger linearer Programmierung für den digitalen Signalprozessor ADSP-2106x. Master’s thesis, Saarland University, 1997.
Kästner, D. and Wilhelm, R. Operations research methods in compiler backends. Mathematical Communications, 1999.
M. Langenbach. CRL — A Uniform Representation for Control Flow. Technical report, Transferbereich 14, Saarland University, November 1998.
R. Leupers. Retargetable Code Generation for Digital Signal Processors. Kluwer Academic Publishers, 1997.
R. Lipsett, C. Schaefer, and C. Ussery. VHDL: Hardware Description and Design. Kluwer Academic Publishers, 12. edition, 1993.
P. Marwedel and G. Goossens. Code Generation for Embedded Processors. Kluwer, 1995.
S. Novack and A. Nicolau. Mutation scheduling: A Unified Approach to Compiling for fine-grain Parallelism. In Languages and Compilers for Parallel Computing, pages 16–30. Springer LNCS, 1994.
L. Nowak. Graph Based Retargetable Microcode Compilation in the MIMÓLA Design System. 20th Annual Workshop on Microprogramming, pages 126–132, 1987.
Philips Electronics North America Corporation. TriMedia TM1000 Preliminary Data Book, 1997.
J. Ruttenberg, G.R. Gao, A. Stoutchinin, and W. Lichtenstein. Software Pipelining Showdown: Optimal vs. Heuristic Methods in a Production Compiler. Proceedings of the PLDI, pages 1–11, 1996.
M.A.R. Saghir, P. Chow, and C.G. Lee. Exploiting Dual Data-Memory Banks in Digital Signal Processors. Proceedings of the ASPLOS, 1996.
A. Sudarsanam. Code Optimization Libraries For Retargetable Compilation For Embedded Digital Signal Processors. PhD thesis, University of Princeton, 1998.
Texas Instruments. TMS320C62xx Programmer’s Guide, 1997.
R. Wilhelm and D. Maurer. Compiler Design. Addison-Wesley, 1995.
H.P. Williams. Model Building in Mathematical Programming. John Wiley and Sons, New York, 3. edition, 1993.
L. Zhang. SILP. Scheduling and Allocating with Integer Linear Programming. PhD thesis, Saarland University, 1996.
V. Zivojnovic, J. M. Velarde, C. Schläger, and H. Meyr. DSPSTONE: A DSP-Oriented Benchmarking Methodology. In Proceedings of the International Conference on Integrated Systems for Signal Processing, 1994.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2000 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Kästner, D. (2000). PROPAN: Ein retargierbares System für Postpassoptimierungen und -analysen. In: Mehlhorn, K., Snelting, G. (eds) Informatik 2000. Informatik aktuell. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-58322-3_17
Download citation
DOI: https://doi.org/10.1007/978-3-642-58322-3_17
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-67880-9
Online ISBN: 978-3-642-58322-3
eBook Packages: Springer Book Archive