Abstract
This paper presents status results of a microprocessor verification project. The authors verify a complete 32-bit RISC microprocessor including the floating point unit and the control logic of the pipeline. The paper describes a formal definition of a “correct” microprocessor. This correctness criterion is proven for an implementation using formal methods. All proofs are verified mechanically by means of the theorem proving system PVS.
supported by the DFG graduate program “Effizienz und Komplexität von Algorithmen und Rechenanlagen’
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References
J.L. Hennessy and D.A. Patterson. Computer Architecture: A Quantitative Approach. Morgan Kaufmann Publishers, INC., San Mateo, CA, 2nd edition, 1996.
D. Cyrluk, S. Rajan, N. Shankar, and M. K. Srivas. Effective theorem proving for hardware verification. In 2nd International Conference on Theorem Provers in Circuit Design, 1994.
Ravi Hosabettu, Ganesh Gopalakrishnan, and Mandayam Srivas. A proof of correctness of a processor implementing Tomasulo’s algorithm without a reorder buffer. In Correct Hardware Design and Verification Methods: IFIP WG 10.5 Internatinal Conference on Correct Hardware Design and Verification Methods (CHARME), pages 8–22. Springer, 1999.
Jun Sawada and Warren A. Hunt. Results of the verification of a complex pipelined machine model. In Correct Hardware Design and Verification Methods: IFIP WG 10.5 Internatinal Conference on Correct Hardware Design and Verification Methods (CHARME), pages 313–316. Springer, 1999.
Matt Kaufmann and J. S. Moore. ACL2: An industrial strength version of nqthm. In Proc. of the Eleventh Annual Conference on Computer Assurance, pages 23–34. IEEE Computer Society Press, 1996.
Thomas A. Henzinger, Shaz Qadeer, and Sriram K. Rajamani. You assume, we guarantee: Methodology and case studies. In Proc. 10th International Conference on Computer-aided Verification (CAV), 1998.
K.L. McMillan. Verification of an implementation of Tomasulo’s algorithm by composition model checking. In Proc. 10th International Conference on Computer Aided Verification, pages 110–121, 1998.
W. Damm and A. Pnueli. Verifying out-of-order executions. In H.F. Li and D.K. Probst, editors, Advances in Hardware Design and Verification: IFIP WG 10.5 Internatinal Conference on Correct Hardware Design and Verification Methods (CHARME), pages 23–47. Chapmann & Hall, 1997.
M.L. McMillan. Verification of infinite state systems by compositional model checking. In Correct Hardware Design and Verification Methods: IFIP WG 10.5 Internatinal Conference on Correct Hardware Design and Verification Methods (CHARME), pages 219–233. Springer, 1999.
Y.-A. Chen and R. E. Bryant. Verification of floating-point adders. Lecture Notes in Computer Science, 1427, 1998.
Y.-A. Chen and R. E. Bryant. PHDD: An efficient graph representation for floating point circuit verification. In IEEE/ACM International Conference on Computer Aided Design; Digest of Technical Papers (ICCAD ′97), pages 2–7, Washington - Brussels - Tokyo, November 1997. IEEE Computer Society Press.
Y.-A. Chen, E. Clarke, P.-H. Ho, and Y. Hoskote. Verification of all circuits in a floating-point unit using word-level model checking. Lecture Notes in Computer Science, 1166, 1996.
M. D. Aagaard and C.-J. H. Seger. The formal verification of a pipelined double-precision IEEE floating-point multiplier. In International Conference on Computer Aided Design, pages 7–10, Los Alamitos, Ca., USA, November 1995. IEEE Computer Society Press.
L. Claesen, D. Verkest, and H. De Man. A proof of the non-restoring division algorithm and its implementation on an ALU. In Formal Methods in System Design, vol. 5, pages 5–31, 1994.
J. O’Leary, M. Leeser, J. Hickey, and M. Aagaard. Non-restoring integer square root: A case study in design by principled optimization. Lecture Notes in Computer Science, 901, 1995.
David M. Russinoff. A mechanically checked proof of IEEE compliance of the floating point multiplication, division and square root algorithms of the AMD-K7 processor. LMS Journal of Computation and Mathematics, 1:148–200, 1998.
Daniel Kröning, Wolfgang Paul, and Silvia M. Müller. Proving the correctness of pipelined micro-architectures. In Klaus Waldschmidt and Christoph Grimm, editors, Proc. of ITG/GI/GMM-Workshop „Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen“, pages 89–98. VDE Verlag, 2000.
Silvia M. Müller and Wolfgang Paul. Computer Architecture: Complexity and Correctness. Springer, 2000.
Institute of Electrical and Electronics Engineers. ANSI/IEEE standard 754-1985, IEEE Standard for Binary Floating-Point Arithmetic, 1985. for a readable account see the article by W.J. Cody et al. in the IEEE MICRO Journal, Aug. 1984, 84–100.
Paul S. Miner. Defining the IEEE-854 floating-point standard in PVS. Technical report, NASA, Langley Research Center, 1995.
Wolfgang Paul. Recherarchitektur II SS98, 1998. Lecture Notes.
Donald E. Thomas and Philip Moorby. The Verilog Hardware Description Language. Kluwer, Boston;Dordrecht;London, 1991.
James C. Hoe and Arvind. Hardware synthesis from term rewriting systems. In Proc. of VLSI ′99, Lisbon, Portugal, 1999.
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Jacobi, C., Kroening, D. (2000). Proving the Correctness of a Complete Microprocessor. In: Mehlhorn, K., Snelting, G. (eds) Informatik 2000. Informatik aktuell. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-58322-3_24
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DOI: https://doi.org/10.1007/978-3-642-58322-3_24
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