Abstract
A new approach for testing VLSI circuits is presented. Through backward critical path tracing, a test and all faults detectable by the test are generated simultaneously. Therefore, the expensive fault simulation is completely eliminated. We present a critical path test generation procedure for digital systems described by hardware description language (HDL). A multiplication circuit described by a HDL is utilized for demonstrating the test generation method.
This work is supported by the U.S. Army Communication Electronics Command under Contract No. DAAB07-82-K-J056.
L. Shen is a visiting scholar at SUNY-Binghamton from Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China.
S.Y.H. Su received a U.S. Senior Scientist Award from the Alexander-von-Humboldt Foundation, Bonn, West Germany, 1984.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
S.Y.H. Su and T. Lin “Functional Testing Techniques for Digital LSI/VLSI Systems” (Invited Paper), Proc. of 21st Design Automation Conference, June 1984.
K.K. Saluja, L. Shen and S.Y.H. Su “A Simplified Algorithm for Testing Microprocessors”, Proc. of 1983 International Test Conference, Oct. 1983, pp. 668–675.
L. Shen and S.Y.H. Su “A Functional Testing Method for Microprocessors”, Proc. of 14th International Symposium on Fault - Tolerant Computing, June 1984.
J.J. Thomas, “Automated Diagnostic Test Programs for Digital Networks”, Computer Design, Aug. 1971, pp. 63–67.
D.T. Wang, “An Algorithm for the Generation of Test Sets for Combinational Logic Networks”, IEEE Trans. on Computers, July 1975, pp. 742–746.
D.T. Wang, “Properties of Faults and Criticalities of Values under Tests for Combinational Networks”, IEEE Trans. on Computers, July 1975, pp. 746–750.
M.A. Breuer and A.D. Friedman, Diagnosis and Reliable Design for Digital Systems, Computer Science Press, 1976, Chapter 2.
M. Abramovici, P.R. Menon and D.T. Miller, “Critical Path Tracing–An Alternative to Fault Simulation”, Proc. of 20th Design Automation Conference, June 1983, pp. 214–220.
Y. Levendel and P.R. Menon, “The *-algorithm; Critical Traces for Functions and CHDL Construct”, Proc. of 13th International Symposium on Fault-Tolerant Computing, June 1983, pp. 90–97.
Y. Levendel and P.R. Menon, “Test Generation Algorithms for Computer Hardware Description Languages”, IEEE Trans: on Computers, July 1982, pp. 577–588.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 1984 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Shen, L., Su, S.Y.H. (1984). VLSI Functional Testing Using Critical Path Traces at a Hardware Description Language Level. In: Großpietsch, KE., Dal Cin, M. (eds) Fehlertolerierende Rechensysteme. Informatik-Fachberichte, vol 84. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-69698-5_30
Download citation
DOI: https://doi.org/10.1007/978-3-642-69698-5_30
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-13348-3
Online ISBN: 978-3-642-69698-5
eBook Packages: Springer Book Archive