Abstract
The object of this paper is to synthetize results that have been published for RAM testing since 1977. These results are concerned with functional and semi-functional testing. It is noted that although the used vocabulary is different, fault hypotheses are very similar. These types of algorithms reached the availability of quasi-optimal algorithms. Structural testing is then introduced, the goal being to relate functional fault hypotheses and structural fault hypotheses, and to investigate the interest of structural type test algorithms compared to functional type test algorithms.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
BASCHIERA D., Courtois B.“Testing for s-on in CMOS”Research report IMAG no RR 439 - March 1984
COURTOIS B.“Failure mechanisms, fault hypotheses and analytical testing on LSI NMOS (HMOS) circuits”VLSI 81 Academic Press, University of Edinburgh, 1981
COURTOIS B., SAHAMI H.“Structural testing of RAMs” Research report IMAG no RR 432, March 1984
GALIAY J., CROUZET Y., VERGNIAULT M. “Physical versus logical fault models MOS LSI circuits: impact on their testability” IEEE Transactions on Computers, vol. C-29 n° 6 pp. 527–531, june 1980
GOLOMB S.W. “Tiling with polyominoes”Journal of combinational Theory n°1, 1966
HAYES J.P. “Detection of pattern-sensitive faults in random aeeess memories” IEEE Transactions on Computers, vol. C-24, n°2, february 1975
MARINESCU M.“Test fonctionnel de mémoire vive à large couverture de pannes” Research report IMAG n° RR 191, march 1980
MARINESCU M.“Simple and efficient algorithms for functional RAM testing” IEEE International Test Conference, november 1982
NAIR R., THATTE S.M., ABRAHAM J.A.“Efficient algorithms for testing semiconductor random access memories” IEEE Transactions on Computers, vol. C-27, n°6, june 1978
NAIR R. “Comments on an optimal algorithm for testing stuck-at faults in random access memories” IEEE Transactions on Computers, vol. C-28, pp.258–261, march 1979
SAHAMI H. “Test analytique de circuits intégrés RAM”Internal report IMAG, june 1982
SUK D.S. “Functional and pattern sensitive fault testing algorithms for semiconductor random access memories” PhD. Thesis, University of Iowa, july 1978
SUK D.S. “An algorithm to detect a class of pattern sensitive faults in semiconductor random access memories” 9th Fault Tolerant Computing Symposium, Madison, june 1979
SUK D.S., REDDY S.M.“Test procedures for a class of pattern sensitive faults in semiconductor random access memories”IEEE Transactions on Computers, vol. C-29, n°6, june 1980
SUCK D.S., REDDY S.M.“A march test for functional faults in semiconductor random access memories” IEEE Transactions on Computers, vol. C-30, n°12, december 1981
TRATTE S.M. “Fault diagnosis of semiconductor random access memories” Coordinated Science Laboratory, University of Illinois, mai 1977
THATTE S.M., ABRAHAM J.A.“Testing of semiconductor random access memories” 7th Fault Tolerant Computing Syposium, Los Angeles, june 1977.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 1984 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Sahami, H., Courtois, B. (1984). Functional Testing Vs. Structural Testing of Rams. In: Großpietsch, KE., Dal Cin, M. (eds) Fehlertolerierende Rechensysteme. Informatik-Fachberichte, vol 84. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-69698-5_32
Download citation
DOI: https://doi.org/10.1007/978-3-642-69698-5_32
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-13348-3
Online ISBN: 978-3-642-69698-5
eBook Packages: Springer Book Archive