Skip to main content
SpringerLink
Log in
Book cover

Architektur und Betrieb von Rechensystemen pp 119–131Cite as

Code Generation and RISC Architectures

  • Conference paper

Part of the book series: Informatik-Fachberichte ((INFORMATIK,volume 168))

Abstract

One of the most important and controversial innovations in computer architecture in the 1980’s has been the notion of a Reduced Instruction Set Computer (RISC). Both the RISC advocates and the defenders of CISC (Complex Instruction Set Computer) architectures argue that the respective styles of architecture are intended to support programming in higher-level languages (HLL’s). The argument for CISC design is that it reduces the “semantic gap” between source language and architecture. The arguments for RISC architecture include the claims that code generation is easier because there are fewer choices, and that the architecture includes only the instructions that are used frequently.

This is a preview of subscription content, log in via an institution.

Chapter
USD   29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD   54.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD   69.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Learn about institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

Bibliography

  1. A. V. Aho and S. C. Johnson, “Optimal Code Generation for Expression Trees”, J. ACM 3 (July 1976), 488–501.

    Google Scholar 

  2. A. V. Aho and M. Ganapathi, “Efficient tree pattern matching: an aid to code generation”, Conf. Rec. 12th ACM Symp. on Prin. of Prog. Lang., Jan. 1985, 334–340.

    Google Scholar 

  3. P. Aigrain, S. L. Graham, R. R. Henry, M. K. McKusick and E. Pelegri-Llopart, “Experience with a Graham-Glanville Style Code Generator”, Proc. SIGPLAN 1984 Symp. on Compiler Const., June 1984.

    Google Scholar 

  4. U. Ammann, “On Code Generation in a PASCAL Compiler”, Software—Practice & Experience 7 (1977), 391–423.

    Article  MATH  Google Scholar 

  5. J. Backus, “The History of Fortran I, II, and III”, in History of Programming Languages, R. Wexelblat (editor), Academic Press, New York, 1981.

    Google Scholar 

  6. C. G. Bell, “RISC.: Back to the Future?”, Datamation 32,11 (1 June 1986).

    Google Scholar 

  7. A. D. Berenbaum, D. R. Ditzel and H. R. McLellan, “Introduction to the CRISP Instruction Set Architecture”, COMPCON, Feb. 24–26 1987.

    Google Scholar 

  8. P. L. Bird, “Register Allocation and Instruction Scheduling for Pipelined SISD Processors”, CRL-Tech. Rep.-12-86, University of Michigan, Ann Arbor, June 1986.

    Google Scholar 

  9. G. J. Chaitin, M. A. Auslander, A. K. Chandra, J. Cocke, M. E. Hopkins and P. W. Markstein, “Register Allocation via Coloring”, J. Computer Lang. 6 (1981), 47–57.

    Article  Google Scholar 

  10. F. Chow and J. L. Hennessy, “Register Allocation by Priority-Based Coloring”, Proc. SIGPLAN 1984 Symp. on Compiler Const., June 1984.

    Google Scholar 

  11. K. D. Cooper, “Analyzing Aliasing of Reference Formal Parameters”, Conf. Rec. 12th ACM Symp. on Prin. of Prog. Lang., Jan. 1985.

    Google Scholar 

  12. D. S. Coutant, C. L. Hammond and J. W. Kelly, “Compilers for the New Generation of Hewlett-Packard Computers”, Proceedings of COMPCON, March 1986, 48–61.

    Google Scholar 

  13. R. N. Faiman and A. A. Kortesoja, “An Optimizing Pascal Compiler”, IEEE Transactions on Software Engineering SE-6 (1980).

    Google Scholar 

  14. C. W. Fraser, “A Knowledge-Based Code Generator Generator.”, Proceedings of the ACM Symposium on Artificial Intelligence and Programming Languages, August 1977.

    Google Scholar 

  15. C. W. Fraser and A. L. Wendt, “Integrating Code Generation and Optimization”, Proc. SIGPLAN Notices 1986 Symp. on Compiler Const., June 1986, 242–248.

    Google Scholar 

  16. M. Ganapathi, C. N. Fischer and J. L. Hennessy, “Retargetable Compiler Code Generation”, Computing Surveys 14,4 (Dec. 1982), 573–592.

    Article  Google Scholar 

  17. M. Ganapathi and C. N. Fischer, “Affix Grammar Driven Code Generation”, Trans. Prog. Lang and Systems 7,4 (Oct. 1985), 560–599.

    Article  Google Scholar 

  18. P. B. Gibbons and S. S. Muchnick, “Efficient Instruction Scheduling for a Pipelined Architecture”, CCC86, June 1986, 11–16.

    Google Scholar 

  19. S. L. Graham, “Table-Driven Code Generation”, IEEE Computer, Aug. 1980, 25.

    Google Scholar 

  20. D. C. Halbert and P. B. Kessler, “Windows of Overlapping Register Frames”, unpublished, June 1980.

    Google Scholar 

  21. J. L. Hennessy and T. R. Gross, “Postpass Code Optimization of Pipeline Constraints”, Trans. Prog. Lang and Systems 5,3 (July 1983), 422–448.

    Article  MATH  Google Scholar 

  22. J. L. Hennessy, “VLSI Processor Architecture”, IEEE Transactions on Computers CSS (December 1984), 1221–1246, IEEE.

    Google Scholar 

  23. R. R. Henry, “Graham Glanville Code Generators”, UCB/Computer Science Dpt. 84/184, Ph.D Dissertation, University of California, Berkeley, 1984.

    Google Scholar 

  24. R. R. Henry and P. C. Damron, “Code Generation Using Tree Pattern Matchers”, Technical Report 87-02-04, University of Washington, Seattle, February 1987.

    Google Scholar 

  25. P. D. Hester, R. O. Simpson and A. Chang, “The IBM RT PC ROMP and Memory Management Unit Architecture”, IBM Publication No. SA23-1057,, IBM Personal Computer Technology, 1986.

    Google Scholar 

  26. U. Kastens, “Code Generation Based on Operator Identification”, manuscript, Universitat-GH Paderborn, 1987.

    Google Scholar 

  27. M. G. H. Katevenis, “Reduced Instruction Set Computer Architectures for VLSI”, Tech. Rep. UCB/Computer Science Dpt. 83/141, PhD Diss., UCB, 1983.

    Google Scholar 

  28. R. Landwehr, H. Jansohn and G. Goos, “Experience with an Automatic Code Generator Generator”, Proc. SIGPLAN 1982 Symp. on Compiler Const., June 1982, 56–66.

    Google Scholar 

  29. J. R. Larus and P. N. Hilfinger, “Register Allocation in the SPUR Lisp Compiler“, Proc. SIGPLAN Notices 1986 Symp. on Compiler Const., June 1986, 255–263.

    Google Scholar 

  30. M. K. McKusick, “Register Allocation and Data Conversion in Machine Independent Code Generators”, 84/214, PhD Diss., Computer Science Division, EECS, UCB, Berkeley, CA, Dec. 1984.

    Google Scholar 

  31. D. A. Patterson and C. H. Sequin, “A VLSI RISC”, IEEE Computer, Sep. 1982.

    Google Scholar 

  32. E. Pelegri-Llopart and S. L. Graham, “Optimal Code Generation for Expression Trees: An Application of BURS Theory”, ACM Symposium on Principles of Programming Languages, San Diego, January 1988.

    Google Scholar 

  33. G. Radin, “The 801 Minicomputer”, Proc. of the Symp. on Arch. Support for Prog. Lang, and Operating Systems, Mar. 1982, 39–47.

    Google Scholar 

  34. L. Semenzato, Lecture, CS265, University of California, Berkeley, October 1987.

    Google Scholar 

  35. R. Sethi and J. D. Ullman, “The Generation of Optimal Code for Arithmetic Expressions”, J. ACM 17,4 (Oct. 1970), 715–728.

    Article  MATH  MathSciNet  Google Scholar 

  36. W. Stallings, ed., Reduced Instruction Set Computers, IEEE, 1986.

    Google Scholar 

  37. P. Steenkiste and J. Hennessy, “LISP on a Reduced-Instruction-Set Processor”, Proceedings of the 1986 Conference on LISP and Functional Programming, Boston, August 1986, 192–201.

    Google Scholar 

  38. A. S. Tanenbaum, “Implications of Structured Programming for Machine Architecture”, Comm. of the ACM 21,3 (Mar. 1978), 237–244.

    Article  MATH  MathSciNet  Google Scholar 

  39. G. S. Taylor, P. N. Hilfinger, J. R. Larus, D. A. Patterson and B. G. Zorn, “Evaluation of the SPUR Lisp Architecture”, Thirteenth International Symposium on Computer Architecture, June 1986.

    Google Scholar 

  40. D. Wall, “Global Register Allocation at Link Time”, Proc. SIGPLAN Notices 1986 Symp. on Compiler Const., June 1986, 264–275.

    Google Scholar 

  41. B. Weisgerber and R. Wilhelm, “Two Tree Pattern Matchers for Code Selection (Including Targeting)”, A 09/86, Universitat des Saarlandes, Saarbrücken, 1986.

    Google Scholar 

  42. W. A. Wulf, R. K. Johnsson, C. B. Weinstock, S. O. Hobbs and C. M. Geschke, The Design of an Optimizing Compiler, North-Holland, New York, NY, 1975.

    MATH  Google Scholar 

  43. W. A. Wulf, “Compilers and Computer Architecture”, IEEE Computer 14,7 (July 1981), 41–48.

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Computer Science Division-EECS, University of California, Berkeley, CA, 94720, USA

    Susan L. Graham

Authors
  1. Susan L. Graham
    View author publications

    You can also search for this author in PubMed Google Scholar

Editor information

Editors and Affiliations

  1. Mathematik-Informatik (FB 17), Universität-Gesamthochschule Paderborn, Warburger Straße 100, 4790, Paderborn, Deutschland

    U. Kastens  & F. J. Rammig  & 

Rights and permissions

Reprints and permissions

Copyright information

© 1988 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

Graham, S.L. (1988). Code Generation and RISC Architectures. In: Kastens, U., Rammig, F.J. (eds) Architektur und Betrieb von Rechensystemen. Informatik-Fachberichte, vol 168. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-73451-9_10

Download citation

  • DOI: https://doi.org/10.1007/978-3-642-73451-9_10

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-18994-7

  • Online ISBN: 978-3-642-73451-9

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics

Search

Navigation