Abstract
In the area of VLSI design testability analysis has become a crucial aspect. Analysis of complex designs can be resonably done only by support of appropriate tools. An advanced method for algorithmic checking the compliance of register transfer and gate level hardware descriptions with testability related design restrictions is presented. Assuming a hierarchical design process, the analysis also is done hierarchically. To increase flexibility, i. e., to handle multiple design restrictions, the particular restrictions are expressed via exchangeable rule sets controlling the analysis. The underlaying method used for analysing is symbolic execution.
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© 1989 Springer-Verlag Berlin Heidelberg
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Glässer, U. (1989). Ein regelbasiertes System zur Testbarkeitsanalyse hierarchisch aufgebauter Schaltungsentwürfe. In: Görke, W., Sörensen, H. (eds) Fehlertolerierende Rechensysteme / Fault-tolerant Computing Systems. Informatik-Fachberichte, vol 214. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-75002-1_27
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DOI: https://doi.org/10.1007/978-3-642-75002-1_27
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-51565-4
Online ISBN: 978-3-642-75002-1
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