Abstract
In this paper we present a fault-tolerant permutation network suitable for VLSI implementation, and distributed algorithms for switch self setting. The network, called Fault-Tolerant Mesh of Trees (FTMT for short), is obtained from Mesh of Trees interconnection scheme, by adding spare links. An n inputs, n outputs FTMT occupies O(n2log2n) area, has O(log n) crossing time, and a constant setting time for its switches, thus leading to an O(log n) overall operational time. So, FTMT is almost optimal in a VLSI setting since O(n2) area and O(log n) time lower bounds for VLSI permutation networks have been established. FTMT works properly even in presence of faulty switches and links. Fault patterns destroying the full access property of the network are studied. Distributed algorithms for switch setting are proposed. We show that such algorithms allow the network to establish the desired I/O connection in O(log n) time whenever the pattern of faulty elements makes it possible.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Broomel G., Heath J.: Classification categories and historical development of circuit switching topologies, ACM Computing Surveys, vol. 15, n. 2 (June 1983), pp. 95–133.
Wu C.L., Feng T.Y.:A VLSI interconnection network for multiprocessor systems, Proc. Compcon, ( Spring 1981 ), pp. 294–298.
ULL84] Ullman J.D.:Computational aspects of VLSI, Computer Science Press, Rockville, Md, 1984
Fault tolerance in VLSI, Special issue of IEEE Proceedings, (May 1986 )
ROS81] Rosenberg A.L.:Three dimensional integrated circuitry, in: VLSI: systems and computations Computer Science Press, Rockville, Md, (1981), pp.69–80
Wu C.L., Feng T.Y. Parallel algorithms to set up the Benes permutation network, IEEE Trans. Comp. vol. 31, n. 2, (Feb. 1982), pp. 148–154
LEI81] Leighton F.T.:New lower bounds techniques for VLSI, Proc. 22nd IEEE Symp. on FOCS, (Oct. 1981), pp. 1–5
Nath D.D., Maheshwari S.N., Bhatt P.C. Efficient VLSI networks for parallel processing based on orthogonal trees, IEEE Trans. Comp., vol 32, n. 6, (June 1983), pp. 569–581
Bertossi, A.A., Bonuccelli M.A.:A VLSI implementation of the symplex algorithm, IEEE Trans. Comp., vol 36, n. 2, (Feb. 1987), pp. 241–247
Grey B.O.A., Avizienis A., Rennels D.A.:A fault tolerant architecture for network storage systems, Proc. 14th FTCS, (June 1984), pp. 232–239
SHE82] Shen J.P.:Fault tolerance analysis of several interconnection networks, Proc. Int. Conf. on Parallel Proc. (1982), pp.102–112
Shen J.P., Hayes J.P.:Fault-tolerance of dynamic-full-access interconnection networks, IEEE Trans. Comp., vol 33, n. 3, (March 1984),pp. 241–248
Adams III G.B., Agrawal D.P., Siegel H.J.: A survey and comparison of fault-tolerant multistage interconnection networks, IEEE Computer Mag., (June 1987), pp. 14–27
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 1989 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Bonuccelli, M.A., Simoncini, L. (1989). A Fault-Tolerant Distributed Control VLSI Permutation Network. In: Görke, W., Sörensen, H. (eds) Fehlertolerierende Rechensysteme / Fault-tolerant Computing Systems. Informatik-Fachberichte, vol 214. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-75002-1_7
Download citation
DOI: https://doi.org/10.1007/978-3-642-75002-1_7
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-51565-4
Online ISBN: 978-3-642-75002-1
eBook Packages: Springer Book Archive