Coding redundancy for combinational switching circuits

Abstract

This paper presents a technique for designing fault tolerant combinational circuits (Fig. 1c) which are functional blocks of a VLSI-system, by means of linear error correcting codes (ECC) to increase the reliablity R(t). This new technique, called CLC (coded logical channels), is a concurrent error detection and correction approach. At first this paper presents the technique for single-output circuits and then it extends this technique to multi-output circuits and compares it with the Triple Modular Redundancy (TMR) technique which uses a restoring organ with a minimal gate count and is therefore a stiff competitor.

This paper refers to a paper [1] which introduced a general method of applying ECC to digital systems. [1] introduced no algorithmic procedure which could be applied to combine ECC and combinational circuits. This paper introduces such a procedure. Therefore it will be possible to generate ECC protected switching functions automatically in a CAD-system.

This work has been developed at the Technische Universität Berlin, Institut für Mikroelektronik, 1000 Berlin 12, Jebensstraße 1