Abstract
In this paper, the encoding/decoding circuitry for various t-unidirectional and burst uni-directional error detecting codes (UEDCs) is studied. Two new realizations of an encoder for all these codes are given. One approach assumes the use of carry-save adders to build a modular counter of 1’s (or 0’s) which is a basic element of an encoder. The new counter is proved to be faster than a commonly used counter built of ripple-carry adders. The second approach is based on the use of a multi-output threshold circuit Tn. With Tn-based encoders the design is easy for any known UEDC. Either encoder proposed here enjoys many advantages which are important for a VLSI implementation, such as: a highly regular structure, easy testability, the least amount of hardware used, and the smallest delay as compared to other similar circuits. Finally, it is shown that an efficient self-testing checker for any UEDC can be built by using the new encoders given here.
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© 1991 Springer-Verlag Berlin Heidelberg
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Piestrak, S.J. (1991). Efficient Encoding/Decoding Circuitry for Systematic Unidirectional Error-Detecting Codes. In: Cin, M.D., Hohl, W. (eds) Fault-Tolerant Computing Systems. Informatik-Fachberichte, vol 283. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-76930-6_16
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DOI: https://doi.org/10.1007/978-3-642-76930-6_16
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