Abstract
When designing VLSI integrated circuit (IC), the regularity of its structure makes the design process simpler. Because of this, IC’s with regular architecture like iterative logic arrays (ILA’s) have attracted the attention of scientists during the last years. However, the simplified IC design is not the only result. The simplified IC testing is very often another advantage. The problem of fault diagnosis in ILA’s consisting of simple combinational cells and implemented in CMOS technology is studied in the paper.
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Heřt, V., van de Goor, A.J. (1991). Truth Table Verification for One-Dimensional CMOS ILA’s. In: Cin, M.D., Hohl, W. (eds) Fault-Tolerant Computing Systems. Informatik-Fachberichte, vol 283. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-76930-6_18
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DOI: https://doi.org/10.1007/978-3-642-76930-6_18
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