Abstract
A method of fault-tolerance in mesh-connected processor arrays is presented. This method is based on a new type of interconnection network called the Interlocking Bus Network. The array can be reconfigured in the presence of faulty processors, using an algorithm for bipartite graph matching. The survivability of this method and its hardware/delay overhead are presented and compared to other schemes. The new technique is very general, leading to a number of important extensions. Application of the method to the BLITZEN parallel computer is also discussed.
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References
R. Michael Hord. The Uliac-IV: The First Supercomputer. Computer Science Press, 1982.
D. Hillis. The Connection Machine. MIT Press, 1985.
K.E. Batcher. Design of a Massively Parallel Processor. IEEE Trans. Comp., C-29:836–840, sep 1980.
D.W. Blevins, E.W. Davis, R.A. Heaton, and J.H. Reif. BLITZEN: A Highly Integrated Massively Parallel Machine. Journal of Parallel and Distributed Computing, pages 150–160, aug 1990.
M. Chean and J.A.B. Fortes. A Taxonomy of Reconfiguration Techniques for Fault-Tolerant Arrays. IEEE Computer, pages 55–69, jan 1990.
R. Negrini, M. G. Sami, and R. Stefanelli. Fault Tolerance Through Reconfiguration in VLSI and WSI Arrays. MIT Press, 1989.
M. Chean and J. A. B. Fortes. Fuss: A reconfiguration scheme for fault-tolerant processor arrays. In Intl. Wkshp. on Hardware Fault Tolerance in Multiprocessors, pages 30–32, June 1989.
K. S. Hedlund and L. Snyder. Wafer-scale integration of configurable, highly-parallel architectures and processors. In Proc. 1982 Intl. Conf. on Parallel Processing, pages 262–264. IEEE Computer Society Press, 1982.
A. Singh. Interstitial Redundancy: An Area Efficient Fault Tolerance Scheme for Large Area VLSI Processor Arrays. IEEE Trans. Comp., C-37(11):1398–1410, nov 1988.
K. Mehlhorn. Data Structures and Algorithms 2: Graph Algorithms and NP-Completeness. Springer-Verlag, 1984.
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© 1991 Springer-Verlag Berlin Heidelberg
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Siegle, M.G., Reeves, D.S., Kozminski, K. (1991). The Interlocking Bus Network For Fault-Tolerant Processor Arrays. In: Cin, M.D., Hohl, W. (eds) Fault-Tolerant Computing Systems. Informatik-Fachberichte, vol 283. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-76930-6_29
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DOI: https://doi.org/10.1007/978-3-642-76930-6_29
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-54545-3
Online ISBN: 978-3-642-76930-6
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