Abstract
Certain application areas of signal processing and machine learning, such as robotics, impose technical limitations on the computing hardware, which make the use of generic processors unfeasible. In this paper we propose a framework for the development of dataflow accelerators as a possible solution. The approach is based on model based development and code generation to allow a rapid development of the accelerators and perform a functional verification of the overall system.
This work was supported by the German Federal Ministry of Economics and Technology (BMWi, grants FKZ 50 RA 1012 and FKZ 50 RA 1011).
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Woehrle, H., Kirchner, F. (2015). Reconfigurable Hardware-Based Acceleration for Machine Learning and Signal Processing. In: Drechsler, R., Kühne, U. (eds) Formal Modeling and Verification of Cyber-Physical Systems. Springer Vieweg, Wiesbaden. https://doi.org/10.1007/978-3-658-09994-7_23
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DOI: https://doi.org/10.1007/978-3-658-09994-7_23
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