Abstract
Hardware prefetching is widely employed in modern processors. It has been proved that prefetching can significantly improve application’s performance unless it exhibits sparse locality. Nevertheless, prefetching may result in performance degradation in CMP systems as it issues many off-chip memory requests. In this paper, we propose MCPref, a prefetching mechanism that is sensitive to the load of memory bus. Unlike traditional prefetching mechanism, MCPref opens when memory bus is starve and halts when memory bus is busy. Simulation results show that our non-feedback prefetcher design is effective in the scenario of multi-core architecture.
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Acknowledgement
This research is supported by 863 Program of China under grant 2012AA010902, by the NSF of China under grant 61133004, 61073011, and 61202425.
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Zhu, D., Wang, R., Luan, Z., Qian, D., Zhang, H., Cai, J. (2015). Memory Centric Hardware Prefetching in Multi-core Processors. In: Yueming, L., Xu, W., Xi, Z. (eds) Trustworthy Computing and Services. ISCTCS 2014. Communications in Computer and Information Science, vol 520. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-662-47401-3_41
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DOI: https://doi.org/10.1007/978-3-662-47401-3_41
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