Abstract
Fault and power attacks are two common ways of extracting secrets from tamper-resistant chips. Although several protections have been proposed to thwart these attacks, resistant designs usually claim significant area or speed overheads. Furthermore, circuit-level countermeasures are usually not reconfigurable at runtime. This paper exploits the AES’ algorithmic features to propose low-cost and low-latency protections. We provide Verilog and FPGA implementation details. Using our design, real-life applications can be configured during runtime to meet the user’s needs and the system’s constraints.
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Notes
- 1.
In that respect see our open question in Sect. 7.
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Acknowledgments
The authors thank Ms. Natacha Laniado (natacha@laniado.fr) for proofreading and correcting this paper.
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Portella do Canto, R., Korkikian, R., Naccache, D. (2016). Buying AES Design Resistance with Speed and Energy. In: Ryan, P., Naccache, D., Quisquater, JJ. (eds) The New Codebreakers. Lecture Notes in Computer Science(), vol 9100. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-662-49301-4_9
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DOI: https://doi.org/10.1007/978-3-662-49301-4_9
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