Skip to main content

Quantum Mechanical Analytical Drain Current Modeling and Simulation for Double Gate FinFET Device Using Quasi Fermi Potential Approach

  • Conference paper
  • 2957 Accesses

Part of the book series: Advances in Intelligent and Soft Computing ((AINSC,volume 131))

Abstract

Quantum mechanical analytical modeling and simulations for calculating the drain current of FinFET devices has been proposed in this paper. The work is presented for a FinFET structure with channel length of 30 nm, Fin height of 30 nm and Fin thickness of 20 nm. The variation of drain current with applied drain voltage and gate voltage for varying channel lengths and Fin thicknesses has also been evaluated with modeling and simulation using quasi Fermi potential approach. Our analytical modeling results were compared and contrasted with the reported experimental results in order to verify our proposed model. A close match was found which validates our analytical approach. The drain current simulations have also been evaluated using the Synopsys TCAD tool Sentaurus and compared with the results obtained through our QM model.

This is a preview of subscription content, log in via an institution.

Buying options

Chapter
USD   29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD   259.00
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD   329.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Learn about institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. Hisamoto, D., Lee, W.-C., Kedzierski, J., Takeuchi, H.: FinFET—A Self-Aligned DG MOSFET Scalable to 20 nm. IEEE Transactions on Electron Devices 47, 2320–2325 (2000)

    Article  Google Scholar 

  2. Swahn, B., Hassoun, S.: Gate Sizing: FinFETs vs 32nm Bulk MOSFETs. In: DAC, pp. 24–28 (2006)

    Google Scholar 

  3. Huang, X., Lee, W.-C., Kuo, C., Hisamoto, D.: Sub-50 nm P-Channel FinFET. IEEE Transactions On Electron Devices 48(5), 880–886 (2001)

    Article  Google Scholar 

  4. Joshi, R.V., Williams, R.Q., Nowak, E., Kim, K., Beintner, J., Ludwig, T., Aller, I., Chuang, C.: FinFET SRAM for high-performance low-power applications. Presented at Proceedings of the 34th European Solid-State Device Research Conference, Leuven, Belgium, pp. 69–72 (2004)

    Google Scholar 

  5. Entner, R., Garnet, A., Grasser, T., Selberherr, S.: A Comparison of Quantum Correction Models for the Three-Dimensional Simulation of FinFET Structures. In: 2th International Spring Seminar on Electronics Technology, pp. 114–117. IEEE (2004)

    Google Scholar 

  6. Choi, Y.-K., Lindert, N., Xuan, P., Tang, S., Ha, D., Anderson, E., King, T.J., Bokor, J., Hu, C.: Sub-20nm CMOS FinFET Technologies. In: IEEE IEDM Technical Digest, pp. 421–424 (2001)

    Google Scholar 

  7. Kim, K., Kwon, O., Seo, J., Won, T.: Nanoscale Device Modeling and Simulation: Fin Field-Effect Transistor (FinFET). Japanese Journal of Applied Physics 43(6B), 3784–3789 (2004)

    Article  Google Scholar 

  8. Munteanu, D., Autran, J.-L., Loussier, X., Cerutti, S.H.R., Skotnicki, T.: Quantum Short-channel Compact Modelling of Drain-Current in Double-Gate MOSFET. Elsevier Solid-State Electronics 50, 680–686 (2006)

    Article  Google Scholar 

  9. Van Overstraeten, R.J., Declerck, G.J., Muls, P.A.: Theory of the MOS transistor in weak inversion-new method to determine the number of surface states. IEEE Trans. Electron Dev. 22(5), 282–288 (1975)

    Article  Google Scholar 

  10. Harrison, S., Munteanu, D., Autran, J.L., Cros, A., Cerutti, R., Skotnicki, T.: Electrical characterization and modeling of high-performance SON DG MOSFETs. In: Proceedings ESSDERC, pp. 373–376 (2004)

    Google Scholar 

  11. Oh, S.-H., Monroe, D., Hergenrother, J.M.: Analytic description of shortchannel effects in fully-depleted Double-Gate and cylindrical, surrounding-gate MOSFETs. IEEE Electron Dev. Lett. 21(9), 445–447 (2000)

    Article  Google Scholar 

  12. Sentaurus Device User Guide, Version- A2007.12, Synopsys Inc.

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Balwinder Raj .

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2012 Springer India Pvt. Ltd.

About this paper

Cite this paper

Raj, B., Saxena, A.K., Dasgupta, S. (2012). Quantum Mechanical Analytical Drain Current Modeling and Simulation for Double Gate FinFET Device Using Quasi Fermi Potential Approach. In: Deep, K., Nagar, A., Pant, M., Bansal, J. (eds) Proceedings of the International Conference on Soft Computing for Problem Solving (SocProS 2011) December 20-22, 2011. Advances in Intelligent and Soft Computing, vol 131. Springer, New Delhi. https://doi.org/10.1007/978-81-322-0491-6_35

Download citation

  • DOI: https://doi.org/10.1007/978-81-322-0491-6_35

  • Publisher Name: Springer, New Delhi

  • Print ISBN: 978-81-322-0490-9

  • Online ISBN: 978-81-322-0491-6

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics