Analyzing Different Mode FinFET Based Memory cell at different power supply for Leakage Reduction

Abstract

FinFET are more versatile than traditional single-gate field effect transistors because it has two gates that can be controlled independently. Usually, the second gate of FinFET is used to dynamically control the threshold voltage of the first gate in order to improve circuit performance and reduce leakage power. A self-controllable-voltage-level (SVL) circuit which can supply a maximum DC voltage to an active-load circuit on request or can decrease the DC voltage supplied to a load circuit in standby mode was developed. This SVL circuit can drastically reduce standby leakage power of CMOS logic circuits with minimal overheads in terms of chip area and speed. In this paper we propose new leakage power reduction techniques namely series LSVL (lower self controlled voltage level) and after using it, leakage power reduces 20 % for every increment of series transistor in lower ground connection. Leakage is found to contribute more amount of total power consumption in power-optimized FinFET logic circuits. This paper mainly deal with the various logic design styles to obtain the Leakage power savings through the judicious use of FinFET logic styles using NOR based design at 45 nm technology. FinFET circuits are superior in performance and produce less static power when compared to 32 nm circuits. FinFET can be designed at 32 nm. Finally, implementation of the schematics in CMOS NOR MODE, SG MODE, IG MODE, IG/LP MODE, LP MODE of NOR based FINFET is simulated by cadence virtuoso tools version 6.1 to obtain Leakage Power and Power Dissipation. By applying this we obtain 88 % Leakage power savings through the judicious use of FinFET logic styles having NOR based design at 45 nm technology.