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Floating Point-based Universal Fused Add–Subtract Unit

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Book cover Proceedings of the Second International Conference on Soft Computing for Problem Solving (SocProS 2012), December 28-30, 2012

Part of the book series: Advances in Intelligent Systems and Computing ((AISC,volume 236))

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Abstract

This paper describes fused floating point add–subtract operations and which is applied to the implementation of fast fourier transform (FFT) processors. The fused operations of an add–subtract unit which can be used both radix-2 and radix-4 butterflies are implemented efficiently with the two fused floating point operations. When placed and routed using a high-performance standard cell technology, the fused FFT butterflies are about may be work fast and gives user-defined facility to modify the butterfly’s structure. Also the numerical results of the fused implementations are more accurate, as they use rounding modes is defined as per user requirement.

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References

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Author information

Authors and Affiliations

  1. Electronics Engineering Deparment, Yeshwantrao Chavan College of Engineering, Nagpur, Maharashtra, India

    Ishan A. Patil & Prasanna Palsodkar

  2. Electronics Engineering Department, Sipna College of Engineering Amravati, Amravati, Maharashtra, India

    Ajay Gurjar

Authors
  1. Ishan A. Patil
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  2. Prasanna Palsodkar
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  3. Ajay Gurjar
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Corresponding author

Correspondence to Ishan A. Patil .

Editor information

Editors and Affiliations

  1. Institute of Engineering and Technology, JK Lakshmipat University, Jaipur, Rajasthan, India

    B. V. Babu

  2. Department of Computer Science, Liverpool Hope University, Liverpool, United Kingdom

    Atulya Nagar

  3. Department of Mathematics, Indian Institute of Technology Roorkee, Roorkee, Uttarakhand, India

    Kusum Deep

  4. Department of Paper Technology, Indian Institute of Technology Roorkee, Roorkee, India

    Millie Pant

  5. Department of Applied Mathematics, South Asian University, New Delhi, India

    Jagdish Chand Bansal

  6. Institute of Engineering and Technology, JK Lakshmipat University, Jaipur, Rajasthan, India

    Kanad Ray

  7. Institute of Engineering and Technology, JK Lakshmipat University, Jaipur, Rajasthan, India

    Umesh Gupta

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Patil, I.A., Palsodkar, P., Gurjar, A. (2014). Floating Point-based Universal Fused Add–Subtract Unit. In: Babu, B., et al. Proceedings of the Second International Conference on Soft Computing for Problem Solving (SocProS 2012), December 28-30, 2012. Advances in Intelligent Systems and Computing, vol 236. Springer, New Delhi. https://doi.org/10.1007/978-81-322-1602-5_29

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  • DOI: https://doi.org/10.1007/978-81-322-1602-5_29

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  • Publisher Name: Springer, New Delhi

  • Print ISBN: 978-81-322-1601-8

  • Online ISBN: 978-81-322-1602-5

  • eBook Packages: EngineeringEngineering (R0)

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