Abstract
The efficiency of the core Galois field arithmetic improves the performance of elliptic curve based public key cryptosystem implementation. This paper describes the design and implementation of a reconfigurable Galois field multiplier, which is implemented using field programmable gate arrays (FPGAs). The multiplier of Galois field based on karatsuba’s divide and conquer algorithm allows for reasonable speedup of the top-level public key algorithms. Binary Karatsuba multiplier is more efficient if it is truncated at n-bit multiplicand level and use an efficient classic multiplier algorithm. In these work three levels to truncate Binary karatsuba algorithm (4 bits, 8 bits and 16 bits) are chosen showing that 8 bits is the best level for minimum number of slices and time delay to truncate Binary karatsuba algorithm which is designed on a Xilinx VirtexE XCV2600 FPGA device. The VHDL hardware models are building using Xilinx ISE foundation software. This work is able to compute GF(2191) multiplication in 45.889 ns.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Batina L., Mentens N., Ors S.B., and Preneel B. Serial Multiplier Architectures over GF(2n) for Elliptic Curve Cryptosystems. In Proceedings of the 12th IEEE Mediterranean Electrotechnical Conference MELECON 2004, volume 2, pages 779-782. IEEE Computer Society, May 2004.
Cheung Ray C.C., Wayne Luk and Cheung Peter Y.K.,” Reconfigurable Elliptic Curve Cryptosystems on a Chip”, Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE’05), IEEE, 2005.
El hadj Youssef Wajih, Guitouni Zied, Machhout Mohsen and Tourki Rached,”Design and Implementation of Elliptic Curve Point Multiplication Processor over GF (2m)”, IJCSES International Journal of Computer Sciences and Engineering Systems, Vol.2, No.2, 2008.
Ernst M., Jung M., and et. al. F. M., “A Reconfigurable System on Chip Implementation for Elliptic Curve Cryptography over GF(2n),” Cryptographic Hardware and Embedded Systems CHES 2002, 4th International Workshop, Redwood Shores, CA, USA, 2002.
Hankerson Darrel, Menezes Alfred and Vanstone Scott,“Guide to Elliptic Curve Cryptography”, Springer, ISBN 038795273,2004.
IEEE P1363. “Standard specifications for public-key cryptography”. Draft Version 7, September 1998.
Lenstra A. and Verheul E., “Selecting Cryptographic Key Sizes,” Proc. Workshop on Practice and Theory in Public Key Cryptography, Springer-Verlag, ISBN 3540669671, pp. 446–465, 2000.
Lopez J. and Dahab R.,” An Overview of Elliptic Curve Cryptography”, Tech. Report, IC-00-10, May 2000.
Lopez J. and Dahab R., “Fast multiplication on elliptic curves over GF(2m) without precomputation”, Proceedings of the First International Workshop on Cryptographic Hardware and Embedded Systems (CHES ’99), Springer-Verlag LNCS 1717, 1999, pp. 316–327, Cancun, Mexico, May 2003.
McEliece R.J, “Finite Fields for Computer Scientists and Engineers, Kluwer Academic Publishers, 1987.
Orlando G. and Paar C., “A Scalable GF(p) Elliptic Curve Processor Architecture for Programmable Hardware,” Cryptographic Hardware and Embedded Systems - CHES 2001, Third International Workshop, Paris, France, May 14-16, 2001, Proceedings, vol. 2162, pp. 348–363,May 2001.
Paar C., Fleischmann P., and Soria-Rodriguez P., “Fast Arithmetic for Public- Key Algorithms in Galois Fields with Composite Exponents”. IEEE Trans.Computers, 48(10): 1025-1034, 1999.
Rodriguez-Henriquez F., Saqib N.A. and Diaz-Pérez A., “A fast parallel Implementation of Elliptic Curve point multiplication over GF(2m)”, Computer Science Section, Electrical Engineering Department, Centro de Investigacion y de Estudios Avanzados del IPN,.Microprocessors and Microsystems, Vol. 28, Issues 5-6, 2 August 2004, pp. 329- 339.
Rodriguez-Henriquez F., Saqib N.A., Diaz-Perez A. and Koc Cetin Kaya, “Cryptographic Algorithms on Reconfigurable Hardware”,Springer, ISBN 0387338837,2006.
Rodriguez-Henriquez F. and Kog. Q. K. “On Fully Parallel Karatsuba Multipliers for GF (2m)”. In International Conference on Computer Science and Technology (CST), pages 405-410, 2003.
Saqib N.A., Rodríguez-Henruez F., and Díaz-Pérez A., “A Reconfigurable Processor for High Speed Point Multiplication in Elliptic Curves,” Int’l J. Embedded Systems, vol. 1, nos. 3/4, 2005.
Sherigar M. B., Mahadevan A. S., Kumar K. S., and David S. A Pipelined Parallel Processor to Implement MD4 Message Digest Algorithm on Xilinx FPGA. In VLSID ’98: Proceedings of the Eleventh International Conference on VLSI Design: VLSI for Signal Processing, page 394, Washington, DC, USA,1998. IEEE Computer Society.
Author information
Authors and Affiliations
Corresponding authors
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2010 Springer Science+Business Media B.V.
About this paper
Cite this paper
El-sisi, A.B., Shohdy, S.M., Ismail, N. (2010). Reconfigurable Implementation of Karatsuba Multiplier for Galois Field in Elliptic Curves. In: Sobh, T., Elleithy, K., Mahmood, A. (eds) Novel Algorithms and Techniques in Telecommunications and Networking. Springer, Dordrecht. https://doi.org/10.1007/978-90-481-3662-9_14
Download citation
DOI: https://doi.org/10.1007/978-90-481-3662-9_14
Published:
Publisher Name: Springer, Dordrecht
Print ISBN: 978-90-481-3661-2
Online ISBN: 978-90-481-3662-9
eBook Packages: EngineeringEngineering (R0)