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Off-Chip SDRAM Access Through Spidergon STNoC

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Book cover VLSI 2010 Annual Symposium

Part of the book series: Lecture Notes in Electrical Engineering ((LNEE,volume 105))

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Abstract

External memory access in MPSoCs becomes more challenging with the growing requirements for high bandwidth and low latency. We propose a novel method for optimizing external memory access in term of latency for NoC-based MPSoCs. Our approach considers the off-chip memory access within a system approach: from the initiators to the memory modules through the NoC-based interconnect. We couple QoS of both NoC and memory scheduler in order to guarantee continued services throughout the request and the response paths, between the masters and the SDRAM modules. We study the influence of low-priority requests over high-priority requests. We also analyze the influence of the number of the conflict points inside the NoC over high-priority requests latency. We compare the use of virtual channels with the physical direct connection to map latency-sensitive IPs requests towards the memory subsystem, and demonstrate that both solutions are equivalent in term of memory access latency.

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Notes

  1. 1.

    Multi Processor System on Chip.

  2. 2.

    System on Chip.

  3. 3.

    Double Date Rate Synchronous Dynamic Random Access Memory.

  4. 4.

    Column Access Strobe.

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Acknowledgments

We would like to express our sincere gratitude to Prof. Frédéric Pétrot of TIMA Laboratory in Grenoble for offering his tremendous experience in the field to promote this work.

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Authors and Affiliations

  1. STMicroelectronics, Grenoble, France

    Khaldon Hassan & Marcello Coppola

Authors
  1. Khaldon Hassan
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  2. Marcello Coppola
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Corresponding author

Correspondence to Khaldon Hassan .

Editor information

Editors and Affiliations

  1. Messolonghi, Dept. Telecommunication Systems &, Technological Educational Institute of, National Road, Nafpaktos, 303 00, Greece

    Nikolaos Voros

  2. School of Electrical Engineering &, Computer Science, University of Central Florida, Central Florida Blvd. 4000, Orlando, 32816-2362, Florida, USA

    Amar Mukherjee

  3. , Informatics & MM, Technological Educational Institute of P, Rhga Feraiou, Pyrgos, 27100, Greece

    Nicolas Sklavos

  4. , Dept. of Computer Science and Technology, University of Peloponnese, Terma Karaiskaki, Tripolis, 22100, Greece

    Konstantinos Masselos

  5. , Institut für Technik der Informationsver, Karlsruhe Institute of Technology, Vinzenz-Priessnitzstr. 1, Karlsruhe, 76131, Germany

    Michael Huebner

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Hassan, K., Coppola, M. (2011). Off-Chip SDRAM Access Through Spidergon STNoC. In: Voros, N., Mukherjee, A., Sklavos, N., Masselos, K., Huebner, M. (eds) VLSI 2010 Annual Symposium. Lecture Notes in Electrical Engineering, vol 105. Springer, Dordrecht. https://doi.org/10.1007/978-94-007-1488-5_15

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  • DOI: https://doi.org/10.1007/978-94-007-1488-5_15

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  • Publisher Name: Springer, Dordrecht

  • Print ISBN: 978-94-007-1487-8

  • Online ISBN: 978-94-007-1488-5

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