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VLSI 2010 Annual Symposium pp 31–45Cite as

Trust Management Through Hardware Means: Design Concerns and Optimizations

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Part of the book series: Lecture Notes in Electrical Engineering ((LNEE,volume 105))

Abstract

Trust in security demanding software platforms is a very important feature. For this reason, Trusted computing group has specified a TPM hardware module that can enforce and guaranty a high trust level to all the platform’s involved entities. However, the TPM’s features can not be fully exploited in systems under extreme physical conditions. To solve this problem, the use of a special purpose hardware module, physically connected to a host security system’s device acting as a local trusted third party, has been proposed in literature. In this chapter, we describe the hardware structure of such a hardware module, called Autonomous Attestation Token (AAT) and discuss hardware resource constrains, security bottlenecks that can stem from improper design of its various components integrated in the AAT’s structure. We conclude that the efficiency of the AAT system is closely related to the efficiency of its public key encryption–decryption unit (RSA encryption–decryption module). In this book chapter, we address these issues by describing a design methodology toward a low hardware resources (small chip covered area) and side channel attack resistant RSA hardware architecture. The described hardware architectures’ implementations provide very optimistic results of very low chip covered area and high computation speed thus verifying the efficiency of the proposed algorithms and architecture design approach.

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Acknowledgements

The work reported in this paper is supported by the European Commission through the SECRICOM FP7 European project under contract FP7 SEC 218123

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Authors and Affiliations

  1. Department of Electrical and Computer Engineering, University of Patras, Rio Campus, Patras, Greece

    Apostolos P. Fournaris

  2. Institute for Applied Information Processing and Communications, Graz University of Technology, Graz, Austria

    Daniel M. Hein

Authors
  1. Apostolos P. Fournaris
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  2. Daniel M. Hein
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Corresponding author

Correspondence to Apostolos P. Fournaris .

Editor information

Editors and Affiliations

  1. Messolonghi, Dept. Telecommunication Systems &, Technological Educational Institute of, National Road, Nafpaktos, 303 00, Greece

    Nikolaos Voros

  2. School of Electrical Engineering &, Computer Science, University of Central Florida, Central Florida Blvd. 4000, Orlando, 32816-2362, Florida, USA

    Amar Mukherjee

  3. , Informatics & MM, Technological Educational Institute of P, Rhga Feraiou, Pyrgos, 27100, Greece

    Nicolas Sklavos

  4. , Dept. of Computer Science and Technology, University of Peloponnese, Terma Karaiskaki, Tripolis, 22100, Greece

    Konstantinos Masselos

  5. , Institut für Technik der Informationsver, Karlsruhe Institute of Technology, Vinzenz-Priessnitzstr. 1, Karlsruhe, 76131, Germany

    Michael Huebner

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Fournaris, A.P., Hein, D.M. (2011). Trust Management Through Hardware Means: Design Concerns and Optimizations. In: Voros, N., Mukherjee, A., Sklavos, N., Masselos, K., Huebner, M. (eds) VLSI 2010 Annual Symposium. Lecture Notes in Electrical Engineering, vol 105. Springer, Dordrecht. https://doi.org/10.1007/978-94-007-1488-5_3

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  • DOI: https://doi.org/10.1007/978-94-007-1488-5_3

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  • Publisher Name: Springer, Dordrecht

  • Print ISBN: 978-94-007-1487-8

  • Online ISBN: 978-94-007-1488-5

  • eBook Packages: EngineeringEngineering (R0)

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