Abstract
This chapter discusses the design and implementation of a streaming-based Connected Component Labeling architecture. The architecture implements a scalable processor, which can be tuned to match the available I/O bandwidth on the computing platform that hosts the hardware. In addition, the chapter presents the hardware performance measurements when implemented on an FPGA platform.
The work presented in this chapter is an extended version of [1], with more focus on the internal design of the Sliced Connected Component Labeling architecture, including a discussion on how the Association FIFO and Coalescing Unit are updated and a description of the CL RAM and Global RAM, which can be found in Sect. 8.5.
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Kumar VS, Irick K, Al Maashri A , Narayanan VK (2010) A Scalable bandwidth aware architecture for connected component labeling, Proceeding ISVLSI
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Acknowledgments
This work was supported in part by NSF awards #0702617 & #0916887, and a scholarship funding from the Government of the Sultanate of Oman.
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Kumar, V.S., Irick, K., Maashri, A.A., Narayanan, V. (2011). A Scalable Bandwidth-Aware Architecture for Connected Component Labeling. In: Voros, N., Mukherjee, A., Sklavos, N., Masselos, K., Huebner, M. (eds) VLSI 2010 Annual Symposium. Lecture Notes in Electrical Engineering, vol 105. Springer, Dordrecht. https://doi.org/10.1007/978-94-007-1488-5_8
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DOI: https://doi.org/10.1007/978-94-007-1488-5_8
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