Design of Configurable Pin Control Block for Multimedia System-on-a-Chip

Abstract

The complexity of generic pin control blocks of multimedia system-on-a-chip (SoC) which implements input/output (I/O) paths for off-chip communication has been increased significantly. Accordingly, the possibility of making human errors in designing this block has been magnified as a new controversy. Generic pin control blocks posses several productivity issues since special register for an additional function and multi-I/O paths are usually fixed at relatively late stage of design activities. Also, generic pin control blocks may have different types of design according to the designer. This feature results in various human errors when we use the traditional RTL description. Thus, this paper presents an approach to reduce human errors based on design automation. In our case study, we succeeded on auto-generating a configurable pin control block in a multimedia SoC platform which has more than 300 generic pins including whether it is an input and output and 900 PAD pins. Ultimately, we reduced the amount of manual description for generating configurable pin control block by 97 %.