Abstract
This paper introduces an enhanced predictor to reduce power consumption for a way-prediction cache used for embedded systems. The proposed predictor shows better prediction accuracy and lower power consumption compared to any conventional data caches. In addition, two representative cache replacement policies, LRU (Least recently Used) and random, are examined for low-power data caches; simulation results show that random reduce power consumption more than LRU for highly-associative way-prediction caches. SimpleScalar and Cacti simulators are used for these simulations with SPEC benchmark programs.
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© 2014 Springer Science+Business Media Dordrecht
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Chu, Y. (2014). A Study for a Low-Power Way Predictor for Embedded Data Caches. In: Huang, YM., Chao, HC., Deng, DJ., Park, J. (eds) Advanced Technologies, Embedded and Multimedia for Human-centric Computing. Lecture Notes in Electrical Engineering, vol 260. Springer, Dordrecht. https://doi.org/10.1007/978-94-007-7262-5_56
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DOI: https://doi.org/10.1007/978-94-007-7262-5_56
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