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Hybrid Optimization Techniques for System-Level Design Space Exploration

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Handbook of Hardware/Software Codesign

Abstract

Embedded system design requires to solve synthesis steps that consist of resource allocation, task binding, data routing, and scheduling. These synthesis steps typically occur several times throughout the entire design cycle and necessitate similar concepts even at different levels of abstraction. In order to cope with the large design space, fully automatic Design Space Exploration (DSE) techniques might be applied. In practice, the high complexity of these synthesis steps requires efficient approaches that also perform well in the presence of stringent design constraints. Those constraints may render vast areas in the search space infeasible with only a fraction of feasible implementations that are sparsely distributed. This is a serious problem for metaheuristics that are popular for DSE of electronic hardware/software systems, since they are faced with large areas of infeasible implementations where no gradual improvement is possible. In this chapter, we present an approach that combines metaheuristic optimization with search algorithms to solve the problem of Hardware/Software Codesign (HSCD) including allocation, binding, and scheduling. This hybrid optimization uses powerful search algorithms to determine feasible implementations This avoids an exploration of infeasible areas and, thus, enables a gradual improvement as required for efficient metaheuristic optimization. Two methods are presented that can be applied to both, problems with linear as well as non-linear constraints, the latter being particularly intended to address aspects such as timeliness or reliability which cannot be approximated by linear constraints in a sound fashion. The chapter is concluded with several examples for a successful use of the introduced techniques in different application domains.

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Abbreviations

BIST:

Built-In Self-Test

DPLL:

Davis-Putnam-Logemann-Loveland

DSE:

Design Space Exploration

EA:

Evolutionary Algorithm

E/E:

Electric and Electronic

ESL:

Electronic System Level

HSCD:

Hardware/Software Codesign

ILP:

Integer Linear Program

MoC:

Model of Computation

MPSoC:

Multi-Processor System-on-Chip

PB:

Pseudo-Boolean

SAT:

Boolean Satisfiability

SMT:

Satisfiability Modulo Theories

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Author information

Authors and Affiliations

  1. Institute of Embedded Systems/Real-Time Systems at Ulm University, Ulm, Germany

    Michael Glaß

  2. Department of Computer Science, Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), Erlangen, Germany

    Jürgen Teich

  3. Robert Bosch GmbH, Corporate Research, Renningen, Germany

    Martin Lukasiewycz

  4. Audi Electronics Venture GmbH, Gaimersheim, Germany

    Felix Reimann

Authors
  1. Michael Glaß
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  2. Jürgen Teich
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  3. Martin Lukasiewycz
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  4. Felix Reimann
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Corresponding author

Correspondence to Michael Glaß .

Editor information

Editors and Affiliations

  1. Department of Computer Science and Engineering, Seoul National University, Seoul, Korea (Republic of)

    Soonhoi Ha

  2. Department of Computer Science, Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), Erlangen, Germany

    Jürgen Teich

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Glaß, M., Teich, J., Lukasiewycz, M., Reimann, F. (2017). Hybrid Optimization Techniques for System-Level Design Space Exploration. In: Ha, S., Teich, J. (eds) Handbook of Hardware/Software Codesign. Springer, Dordrecht. https://doi.org/10.1007/978-94-017-7267-9_8

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