Abstract
This work presents a macro modeling approach for semi-digital smart integrated circuits. The proposed macro model models the behavior of the key circuit block used for semi-digital smart integrated circuits which is the time-to-voltage converter. Furthermore, the macro model can accurately analyze the non-idealities and error sources which can be used as the guideline for design optimization and calibration scheme implantation of semi-digital smart integrated circuits.
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© 2014 Springer Science+Business Media Dordrecht
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Hoseini, Z., Lee, KS., Kim, BG. (2014). Macro Modeling Approach for Semi-digital Smart Integrated Circuits. In: Park, J., Zomaya, A., Jeong, HY., Obaidat, M. (eds) Frontier and Innovation in Future Computing and Communications. Lecture Notes in Electrical Engineering, vol 301. Springer, Dordrecht. https://doi.org/10.1007/978-94-017-8798-7_35
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DOI: https://doi.org/10.1007/978-94-017-8798-7_35
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Online ISBN: 978-94-017-8798-7
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