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A Cost Effective Technique for Diagnosis of Scan Chain Faults

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VLSI Design and Test (VDAT 2017)

Part of the book series: Communications in Computer and Information Science ((CCIS,volume 711))

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Abstract

Scan based diagnosis plays a critical role in failure mode analysis for yield improvement. However, as the logic circuitry associated with scan chains constitute a significant fraction of a chip’s total area the scan chain itself can be subject to defects. In some cases, it has been observed that scan chain failures may account up to \(50\%\) of total chip failures. Hence, scan chain testing and diagnosis have become very crucial in recent years. This paper proposes a hardware-assisted low complexity and area efficient scan chain diagnosis technique. The proposed technique is simple to implement and provides maximum diagnostic resolution for stuck-at faults. The proposed technique can be further extended to diagnose scan chain’s timing faults.

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Correspondence to Jaynarayan Tudu .

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Ahlawat, S., Vaghani, D., Tudu, J., Suhag, A. (2017). A Cost Effective Technique for Diagnosis of Scan Chain Faults. In: Kaushik, B., Dasgupta, S., Singh, V. (eds) VLSI Design and Test. VDAT 2017. Communications in Computer and Information Science, vol 711. Springer, Singapore. https://doi.org/10.1007/978-981-10-7470-7_20

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  • DOI: https://doi.org/10.1007/978-981-10-7470-7_20

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  • Publisher Name: Springer, Singapore

  • Print ISBN: 978-981-10-7469-1

  • Online ISBN: 978-981-10-7470-7

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