Performance Analysis of Disability Based Fault Tolerance Techniques for Permanent Faults in Chip Multiprocessors

Abstract

Dynamic Voltage and Frequency Scaling (DVFS) for reducing power dissipation in Multicore Chips causes cell failure in Cache Memory. Various fault tolerance techniques have been introduced and the analysis of their impacts becomes necessary. Keeping the lowest overhead of Disabling techniques in mind, this work attempts to analyse its performance in Multicore Chips. The parameter Expected Miss Ratio for Multicore $(EMR_{MC})$ as a function of Probability of Cell Failure ($P_{fail}$) is proposed and evaluated. Simulation on Singlecore and Multicore system configuration is done separately to compare the results. It is observed that the Expected Miss Ratio is hardly affected below the lower bound of $P_{fail}$ i.e. 1e-5 where $EMR_{MC}$ remains lower than Expected Miss Ratio for Singlecore($EMR_{SC}$) with a static difference. Above the lower bound, both $EMR_{SC}$ and $EMR_{MC}$ starts increasing and for $P_{fail}$ higher than 1e-3 i.e. the upper bound, $EMR_{MC}$ often converges with $EMR_{SC}$. Within these bounds, $EMR_{MC}$ remains up to 19.3% lower than the $EMR_{SC}$.