Abstract
Energy efficient buffer circuits enable high speed and reliable information transfer among sub-systems of System on Chip (SoC). A novel buffer circuit design exploiting the steep slope characteristics of tunnel FETs (TFET) has been proposed and benchmarked with 20 nm Si FinFET technology. The analysis is performed considering the parameters such as iso-area, iso-energy, iso-speed and noise margins for energy efficiency and reliability. It is clearly evident that TFET buffers exhibit improved speed of operation and high energy efficiency over FinFET buffers for scaled supply voltages, demonstrating suitability for applications such as Internet of things (IoT) SoCs. To further exemplify the buffer circuit performance, TFET/FinFET pass transistor based full adder carry circuit is implemented whose output load is driven by TFET/FinFET buffer. Unlike FinFET buffer circuits, TFET buffers prove to be reliable and energy efficient in driving larger loads despite the area overhead caused due to the unidirectional current conduction of TFETs.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Cristoloveanu, S., Wan, J., Zaslavsky, A.: A review of sharp-switching devices for ultra-low power applications. IEEE J. Electron Devices Soc. 4(5), 215–226 (2016)
Pandey, R., Mookerjea, S., Datta, S.: Opportunities and challenges of tunnel FETs. IEEE Trans. Circuits Syst.-I 63(12), 2128–2138 (2016)
Morris, D.H., Vaidyanathan, K., Avci, U.E., Liu, H., Karnik, T., Young, I.A.: Enabling high-performance heterogeneous TFET/CMOS logic with novel circuits using TFET unidirectionality and low-VDD operation In: IEEE Symposium on VLSI Technology, pp. 1–2, June 2016
Nunez, J., Avedillo, M.: Comparative analysis of projected tunnel and CMOS transistors for different logic application areas. IEEE Trans. Electron Devices 63(12), 5012–5020 (2016)
Kaushal, G., Subramanyam, K., Rao, S.N., Vidya, G., Ramya, R., Shaik, S., Vaddi, R.: Design and performance benchmarking of steep-slope tunnel transistors for low voltage digital and analog circuits enabling self-powered SoCs In: IEEE International Conference on SoC Design (ISOCC), pp. 32–33, November 2014
Choi, W.Y.: Miller effect suppression of tunnel field-effect transistors (TFETs) using capacitor neutralization. IET Electron. Lett. 52(8), 659–661 (2016)
Abdi, D., Kumar, M.J.: Controlling ambipolar current in tunneling FETs using overlapping gate-on-drain. IEEE J. Electron Devices Soc. 2(6), 187–190 (2014)
Sahay, S., Kumar, M.J.: Controlling the drain side tunneling width to reduce ambipolar current in tunnel FETs using hetero dielectric BOX. IEEE Trans. Electron Devices 62(11), 3882–3886 (2015)
Pal, A., Sachid, A., Gossner, H., Rao, V.R.: Insights into the design and optimization of tunnel-FET devices and circuits. IEEE Trans. Electron Devices 58(4), 1045–1053 (2011)
Subramanyam, K., Shaik, S., Vaddi, R.: Tunnel FET based low voltage static vs dynamic logic families for energy efficiency. In: IEEE International Symposium on VLSI Design and Test, pp. 1–2, August 2014
Shaik, S., Krishna, K.S.R., Vaddi, R.: Circuit and architectural co-design for reliable adder cells with steep slope tunnel transistors for energy efficient computing. In IEEE International Conference on VLSI Design and Embedded Systems (VLSID), pp. 306–311, January 2016
Cavalheiro, D., Moll, F., Valtchev, S.: Insights into tunnel FET-based charge pumps and rectifiers for energy harvesting applications. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 25(3), 988–997 (2017)
Sedighi, B., HU, X.S., Liu, H., Nahas, J., Niemier, M.: Analog circuit design using tunnel-FETs. IEEE Trans. Circuits Syst. I Regul. Pap. 62(1), 39–48 (2015)
Liu, H., Vaddi, R., Narayanan, V., Datta, S.: Power rectifier using tunneling field effect transistor, U.S. Patent, 12 July 2016
Penn State University: Verilog-A Models for Heterojunction Tunnel FETs. http://www.ndcl.ee.psu.edu/downloads.asp
Vallabhaneni, H., Japa, A., Shaik, S., Krishna, K.S.R., Vaddi R.: Designing energy efficient logic gates with hetero junction tunnel FETs at 20 nm. In: IEEE Transaction on Electron Devices sponsored Device, Circuit, System Conference, India, pp. 1–5 (2014)
Liu, H., Li, X., Vaddi, R., Ma, K., Datta, S., Narayanan, V.: Tunnel FET RF rectifier design for energy harvesting applications. IEEE J. Emerg. Sel. Top. Circuits Syst. 4(4), 400–411 (2014)
Japa, A., Vallabhaneni, H., Vaddi, R.: Reliability enhancement of a steep slope tunnel transistor based ring oscillator designs with circuit interaction. IET Circuits Devices Syst. 10(6), 522–527 (2016)
Kim, S.H., Jacobson, Z., Patel, P., Hu, C., Liu, T.-J.K.: Tunnel FET based pass-transistor logic for ultra-low power applications. In: 2011 IEEE Device Research Conference (DRC), pp. 133–134, June 2011
Rabaey, J.M., Chandrakasan, A., Nikolic, B.: Digital Integrated Circuits: A Design Perspective, 2nd edn. Prentice Hall, Upper Saddle River (2002)
Acknowledgement
The authors would like to thank the funding support from Department of Science and Technology (DST) SERC young scientist grant NO: SBFTP/ETA-0101/2014.
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2017 Springer Nature Singapore Pte Ltd.
About this paper
Cite this paper
Aditya, J., Harshita, V., Vaddi, R. (2017). Exploiting Characteristics of Steep Slope Tunnel Transistors Towards Energy Efficient and Reliable Buffer Designs for IoT SoCs. In: Kaushik, B., Dasgupta, S., Singh, V. (eds) VLSI Design and Test. VDAT 2017. Communications in Computer and Information Science, vol 711. Springer, Singapore. https://doi.org/10.1007/978-981-10-7470-7_26
Download citation
DOI: https://doi.org/10.1007/978-981-10-7470-7_26
Published:
Publisher Name: Springer, Singapore
Print ISBN: 978-981-10-7469-1
Online ISBN: 978-981-10-7470-7
eBook Packages: Computer ScienceComputer Science (R0)