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International Symposium on VLSI Design and Test

VDAT 2017: VLSI Design and Test pp 545–556Cite as

Effectiveness of High Permittivity Spacer for Underlap Regions of Wavy-Junctionless FinFET at 22 nm Node and Scaling Short Channel Effects

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Part of the book series: Communications in Computer and Information Science ((CCIS,volume 711))

Abstract

In this work, an attempt has been made to investigate the performance of a new device, Wavy Junctionless FinFET at 22 nm node using low to high permittivity spacer for underlap regions. An alternative V TH extraction method has been demonstrated, which signifies the importance of cannel length at the nanoscale regime. The device layer Silicon film possesses uniform doping profile, where the current is controlled by channel doping and the mobility of charge carriers which account the bulk conduction instead of surface conduction. Due to the scalability of device dimensions, underlap regions are preferred to differentiate the control and the location of dopant atoms along the conduction region and hence this enhances the device performances. The simulation results enlighten the effectiveness of high permittivity of spacer region through performance evaluation. The simulated results exhibit an SS of 64 mV/decade, DIBL of 26 mV/V and I ON/I OFF ratio of 107.

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Authors and Affiliations

  1. School of Electronics Engineering, KIIT University, Bhubaneshwar, India

    B. Vandana, J. K. Das & S. K. Mohapatra

  2. Department of Electronics and Communication Engineering, Indian Institute of Technology-Roorkee, Roorkee, India

    B. K. Kaushik

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  1. B. Vandana
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  2. J. K. Das
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  3. S. K. Mohapatra
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  4. B. K. Kaushik
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Correspondence to B. Vandana .

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Editors and Affiliations

  1. Indian Institute of Technology Roorkee, Roorkee, India

    Brajesh Kumar Kaushik

  2. Indian Institute of Technology Roorkee, Roorkee, India

    Sudeb Dasgupta

  3. Indian Institute of Technology Bombay, Mumbai, India

    Virendra Singh

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Vandana, B., Das, J.K., Mohapatra, S.K., Kaushik, B.K. (2017). Effectiveness of High Permittivity Spacer for Underlap Regions of Wavy-Junctionless FinFET at 22 nm Node and Scaling Short Channel Effects. In: Kaushik, B., Dasgupta, S., Singh, V. (eds) VLSI Design and Test. VDAT 2017. Communications in Computer and Information Science, vol 711. Springer, Singapore. https://doi.org/10.1007/978-981-10-7470-7_53

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  • DOI: https://doi.org/10.1007/978-981-10-7470-7_53

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