Abstract
This paper presents design and implementation of LVDS Receiver chip in SCL’s CMOS 0.18 µm, 3.3 V process. It is compatible with Low Voltage Differential Signaling (LVDS) standard. The receiver is designed for data rate of 1Gbps. This chip consists of four channels of LVDS receiver. The size of the chip is 2130 µm × 1500 µm and is packaged in 16 pin CFP (ceramic flat pack) package. The chip architecture, design, measured results are presented here. The radiation test such as total ionizing dose (TID) upto 300 K rad is performed on chip and single event effects (SEE) test using heavy ions Nickel (Ni58) and Silver (Ag107) has also been carried out. The performance under radiation environment is also been given.
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Acknowledgement
The authors also wish to acknowledge the contribution of Gourav Srivastav, Sachin Sharma, Th. Gurmeet Singh, Sunil Bhatnagar from Semi-Conductor Laboratory, Chandigarh (India) during various stages of testing and packaging.
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Malik, M., Kumar, A., Jatana, H.S. (2017). Design & Development of High Speed LVDS Receiver with Cold-Spare Feature in SCL’s 0.18 µm CMOS Process. In: Kaushik, B., Dasgupta, S., Singh, V. (eds) VLSI Design and Test. VDAT 2017. Communications in Computer and Information Science, vol 711. Springer, Singapore. https://doi.org/10.1007/978-981-10-7470-7_63
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DOI: https://doi.org/10.1007/978-981-10-7470-7_63
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