Abstract
Traditionally, VLSI standard cell placement has been driven by hypergraph partitioning tools such as hMetis and MLPart, which employ FM based partitioning. According to the results seen in recent ISPD placement contests, none of the partition driven placers could produce a good solution. Hence, there is a room for improvement of hypergraph partitioning algorithms. In this paper, we present a novel hypergraph partitioning algorithm, which is based on nonlinear optimization. We solve nonlinear equations to partition the hypergraphs in ISPD98 benchmarks. Our results show an improvement over well-known FM heuristic. Our algorithm outperforms FM in 17 benchmarks out of 18, and an average improvement of 111.5% in the quality the of cuts.
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Pawanekar, S., Trivedi, G. (2017). Analytical Partitioning: Improvement over FM. In: Kaushik, B., Dasgupta, S., Singh, V. (eds) VLSI Design and Test. VDAT 2017. Communications in Computer and Information Science, vol 711. Springer, Singapore. https://doi.org/10.1007/978-981-10-7470-7_67
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DOI: https://doi.org/10.1007/978-981-10-7470-7_67
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