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A New Multi-objective Hardware-Software-Partitioning Algorithmic Approach for High Speed Applications

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VLSI Design and Test (VDAT 2017)

Part of the book series: Communications in Computer and Information Science ((CCIS,volume 711))

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Abstract

Designing embedded systems efficiently has always been of significant interest. This has tremendously scaled-up for contemporary applications with their increasing complexity and the need to satisfy multiple conflicting constraints. This paper presents a high-speed Hardware Software Partitioning (HSP) technique for the design of such systems. The Partitioning problem has been modeled as a multi-dimensional optimization problem with the aim of minimizing the area utilization, power dissipation, time of execution and system memory requirement of the implementation. A two-phased algorithm has been proposed which also takes into consideration the communication costs between hardware and software Processing-Engines (PEs) while partitioning. Detailed empirical analysis of the proposed algorithm is presented to ascertain its efficiency, quality and speed.

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References

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Correspondence to Rahul Shrestha .

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© 2017 Springer Nature Singapore Pte Ltd.

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Govil, N., Shrestha, R., Roy Chowdhury, S. (2017). A New Multi-objective Hardware-Software-Partitioning Algorithmic Approach for High Speed Applications. In: Kaushik, B., Dasgupta, S., Singh, V. (eds) VLSI Design and Test. VDAT 2017. Communications in Computer and Information Science, vol 711. Springer, Singapore. https://doi.org/10.1007/978-981-10-7470-7_7

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  • DOI: https://doi.org/10.1007/978-981-10-7470-7_7

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  • Publisher Name: Springer, Singapore

  • Print ISBN: 978-981-10-7469-1

  • Online ISBN: 978-981-10-7470-7

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