Abstract
Dynamic circuits are widely used in high-speed circuit. However, dynamic circuits are very vulnerable to soft errors. An analytical model of critical charge for vulnerable nodes of dynamic circuits is developed. As the accurate model is too complex to calculate, a simplified efficient model is proposed by using an approximate method. Proposed model are verified by SPICE simulation and error analysis respectively. Results demonstrate that these models have high accuracy and can be used both in the efficient analysis and automatic CAD tools.
This work was supported by the National High-Tech Research and Development Program of China (No. 2015AA01A301), the National Natural Science Foundation of China (No. 61303069), and the Ministry of Education Doctoral Foundation of China (No. 20124307110016).
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References
Kumar, J., Tahoori, M.B.: A low power soft error suppression technique for dynamic logic. In: 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 454–462 (2005)
Cha, H., Patel, J.H.: A logic-level model for \(\alpha \)-particle hits in CMOS circuits. In: IEEE International Conference on Computer Design, pp. 538–542 (1993)
Naseer, R., Draper, J., Boulghassoul, Y., Dasgupta, S., Witulski, A.: Critical charge and SET pulse widths for combinational logic in commercial 90 nm CMOS technology. In: ACM Great Lakes Symposium on VLSI, pp. 227–230 (2007)
Rossi, D., Cazeaux, J.M., Omana, M., Metra, C., Chatterjee, A.: Accurate linear model for SET critical charge estimation. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 17, 1161–1166 (2009)
Raji, M., Ghavami, B.: Soft error rate reduction of combinational circuits using gate sizing in the presence of process variations. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 25, 247–260 (2017)
Shivakumar, P., Kistler, M., Keckler, S.W., Burger, D., Alvisi, L.: Modeling the effect of technology trends on the soft error rate of combinational logic. In: International Conference on Dependable Systems and Networks, pp. 389–398 (2002)
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Sun, Y., Cao, Y., Li, J., Li, T. (2018). An Efficient Model for Soft Error Vulnerability of Dynamic Circuits. In: Xu, W., Xiao, L., Li, J., Zhang, C., Zhu, Z. (eds) Computer Engineering and Technology. NCCET 2017. Communications in Computer and Information Science, vol 600. Springer, Singapore. https://doi.org/10.1007/978-981-10-7844-6_13
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DOI: https://doi.org/10.1007/978-981-10-7844-6_13
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