Hardware Implementation and Optimization of Tiny-YOLO Network

Abstract

Convolutional Neural Networks (CNNs) have achieved extraordinary performance in image processing fields. However, CNNs are both computational intensive and memory intensive, making them difficult to be deployed on hardware devices like embedded systems. Although lots of existing work has explored hardware implementation of CNNs, the crucial problem of either inefficient or incomplete still remains. Consequently, in this paper, we propose a design that is highly paralleled to perform efficient computation of CNNs. Furthermore, compared with previous work that rarely takes Fully-Connected (FC) layers into consideration, our work also does well in FC optimization.

We take Tiny-YOLO, an object detection architecture, as the target network to be implemented on an FPGA platform. In order to reduce computing time, we exploit an efficient and generic computing engine that has 64 duplicated Processing Elements (PEs) working simultaneously. Inside each PE, 32 MAC operations are executed in a pipeline manner for further parallelism. Then, for the purpose of reducing memory footprint, we take full advantage of data reusing and data sharing. For example, in our design, parallel PEs share the same input data and on-chip buffers are leveraged to cache data and weights for further reuse. Finally, we apply SVD to FC layers, which decreases 80.6% memory access and computing operations while maintaining comparable accuracy. With these optimizing approaches, our design achieves a detecting rate of over 20 FPS and gets a processing performance of 48 GMACS under 143 MHz working frequency.