Abstract
NAND flash memories are not error-free. The Program/Erase cycles and retention time are two major factors affecting the reliability of NAND flash memories. Most error control codes (ECC) used in a flash memories provide a uniform protection regardless of the different raw bit error rate (RBER) of different storage cells, which fails to take full advantage of the limited available redundancy. To optimize the redundancy and take the unequal RBER into account, an unequal error protection scheme is proposed in this paper to improve the performance of NAND flash. Simulation shows that UEP method is more flexible and performs better in most condition.
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsReferences
Yang, C., Muckatira, D., Kulkarni, A., Chakrabarti, C.: Data storage time sensitive ECC schemes for MLC NAND flash memories. In: 2013 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), pp. 2513–2517. IEEE (2013)
Yuan, L., Liu, H., Jia, P., Yang, Y.: Reliability-based ECC system for adaptive protection of NAND flash memories. In: 2015 Fifth International Conference on Communication Systems and Network Technologies (CSNT), pp. 897–902. IEEE (2015)
Li, J., Zhao, K., Ma, J., Zhang, T.: Realizing unequal error correction for nand flash memory at minimal read latency overhead. IEEE Trans. Circuits Syst. II Express Briefs 61(5), 354–358 (2014)
Cai, Y., Haratsch, E.F., Mutlu, O., Mai, K.: Error patterns in MLC NAND flash memory: measurement, characterization, and analysis. In: Proceedings of the Conference on Design, Automation and Test in Europe, pp. 521–526. EDA Consortium (2012)
Xiao-Bo, J., Xue-Qing, T., Wei-Pei, H.: Novel ECC structure and evaluation method for NAND flash memory. In: 2015 28th IEEE International System-on-Chip Conference (SOCC), pp. 100–104. IEEE (2015)
Liu, W., Rho, J., Sung, W.: Low-power high-throughput bch error correction VLSI design for multi-level cell NAND flash memories. In: IEEE Workshop on Signal Processing Systems Design and Implementation, SIPS 2006, pp. 303–308. IEEE (2006)
Sun, F., Devarajan, S., Rose, K., Zhang, T.: Design of on-chip error correction systems for multilevel NOR and NAND flash memories. IET Circuits Devices Syst. 1(3), 241–249 (2007)
Kim, J., Cho, J., Sung, W.: A high-speed layered min-sum LDPC decoder for error correction of NAND flash memories. In: 2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 1–4. IEEE (2011)
Lee, Y.: Hardware optimizations of hard-decision ECC decoders for MLC NAND flash memories. In: 2015 International SoC Design Conference (ISOCC), pp. 133–134. IEEE (2015)
Mutyam, M., Wang, F., Krishnan, R., Narayanan, V., Kandemir, M., Xie, Y., Irwin, M.J.: Process-variation-aware adaptive cache architecture and management. IEEE Trans. Comput. 58(7), 865–877 (2009)
Paul, S., Cai, F., Zhang, X., Bhunia, S.: Reliability-driven ecc allocation for multiple bit error resilience in processor cache. IEEE Trans. Comput. 60(1), 20–34 (2011)
Yuan, L., Liu, H., Jia, P., Yang, Y.: An adaptive ECC scheme for dynamic protection of NAND flash memories. In: 2015 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), pp. 1052–1055. IEEE (2015)
Geunyeong, Y., Moon, J.: Concatenated raptor codes in nand flash memory. IEEE J. Sel. Areas Commun. 32(5), 857–869 (2014)
Di Carlo, S., Fabiano, M., Piazza, R., Prinetto, P.: Exploring modeling and testing of NAND flash memories. In: 2010 East-West Design & Test Symposium (EWDTS), pp. 47–50. IEEE (2010)
Sun, H., Grayson, P., Wood, B.: Quantifying reliability of solid-state storage from multiple aspects. Proc. SNAPI 11 (2011)
Park, H., Kim, J., Choi, J., Lee, D., Noh, S.H.: Incremental redundancy to reduce data retention errors in flash-based SSDS. In: 2015 31st Symposium on Mass Storage Systems and Technologies (MSST), pp. 1–13. IEEE (2015)
Shokrollahi, A.: Raptor codes. IEEE Trans. Inf. Theory 52(6), 2551–2567 (2006)
Kokkinos, V., Papazois, A., Bouras, C., Kanakis, N.: Evaluating RaptorQ FEC over 3GPP multicast services. In: 2012 8th International Wireless communications and mobile computing conference (IWCMC), pp. 257–262. IEEE (2012)
Mielke, N., Marquart, T., Wu, N., Kessenich, J., Belgal, H., Schares, E., Trivedi, F., Goodness, E., Nevill, L.R.: Bit error rate in NAND flash memories. In: IEEE International Reliability Physics Symposium, IRPS 2008, pp. 9–19 (2008)
Acknowledgement
This paper is supported in part by National Natural Science Foundation of China (61650101), National High Technology Research and Development Program (863 Program: 2015AA015802), Scientific and Innovative Action Plan of Shanghai (15DZ1100100). Yiling Xu from Shanghai Jiao Tong University is the corresponding author of this paper.
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2018 Springer Nature Singapore Pte Ltd.
About this paper
Cite this paper
Lu, D., Xu, Y., Chen, H., Jiang, Z., Zhang, W., Liu, N. (2018). Performance Enhancement of NAND Flash Using Unequal Error Protection. In: Zhai, G., Zhou, J., Yang, X. (eds) Digital TV and Wireless Multimedia Communication. IFTC 2017. Communications in Computer and Information Science, vol 815. Springer, Singapore. https://doi.org/10.1007/978-981-10-8108-8_34
Download citation
DOI: https://doi.org/10.1007/978-981-10-8108-8_34
Published:
Publisher Name: Springer, Singapore
Print ISBN: 978-981-10-8107-1
Online ISBN: 978-981-10-8108-8
eBook Packages: Computer ScienceComputer Science (R0)