Abstract
Advanced Encryption Standard (AES) has been adopted widely in most security protocols due to its robustness till date. It would thus serve well in IoT technology for controlling the threats posed by unethical hackers. This paper presents a hardware-based implementation of the AES algorithm. We present a four-stage pipelined architecture of the encryption and key generation. This method allowed a total plaintext size of 512 bits to be encrypted in 46 cycles. The proposed hardware design achieved a maximum frequency of 1.18 GHz yielding a throughput of 13 Gbps and 800 MHz yielding a throughput of 8.9 Gbps on the 65 and 180 nm processes respectively.
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Acknowledgements
This research was supported by the MSI (Ministry of Science, ICT and Future Planning), Korea, under the Global IT Talent support program (IITP-2017-0-01681) and Human Resource Development Project for Brain scouting program (IITP-2016-0-00352) supervised by the IITP (Institute for Information and Communication Technology Promotion).
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Antwi, A.O.A., Ryoo, K. (2019). Efficient Integrated Circuit Design for High Throughput AES. In: Park, J., Loia, V., Choo, KK., Yi, G. (eds) Advanced Multimedia and Ubiquitous Engineering. MUE FutureTech 2018 2018. Lecture Notes in Electrical Engineering, vol 518. Springer, Singapore. https://doi.org/10.1007/978-981-13-1328-8_54
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DOI: https://doi.org/10.1007/978-981-13-1328-8_54
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