Skip to main content

Analysis of Circuits for Security Using Logic Encryption

  • Conference paper
  • First Online:
Security in Computing and Communications (SSCC 2018)

Part of the book series: Communications in Computer and Information Science ((CCIS,volume 969))

Included in the following conference series:

Abstract

Logic encryption is a technique to protect the design from several security vulnerabilities. Strength of the security depends on the nodes chosen for encryption. Fault Impact based node selection is one of the techniques used in encryption. Here, the hamming distance of various circuits on giving wrong key to the encryption module have been analyzed. Circuits are analyzed for both fault impact based node selection and connectivity based selection. Some of the circuits give better hamming distance for the fault impact based node selection and some for connectivity based selection. So, the selection of nodes depends on various factors and is unique for circuit.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 84.99
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 109.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

References

  1. Rostami, M., Koushanfar, F., Rajendran, J., Karri, R.: Hardware security: threat models and metrics. In: Proceedings of the International Conference on Computer-Aided Design, pp. 819–823 (2013)

    Google Scholar 

  2. Rajendran, J., et al.: Fault analysis-based logic encryption. IEEE Trans. Comput. 64(2), 410–424 (2015)

    Article  MathSciNet  Google Scholar 

  3. Roy, J.A., Koushanfar, F., Markov, I.L.: EPIC: ending piracy of integrated circuits. In: DATE, pp. 1069–1074. IEEE (2008)

    Google Scholar 

  4. Huang, J.; Lach, J.: IC activation and user authentication for security-sensitive systems. In: Proceedings of the 2008 IEEE International Workshop on Hardware-Oriented Security and Trust, Anaheim, CA, USA, pp. 76–80, 9 June 2008

    Google Scholar 

  5. Rajendran, J., Sinanoglu, O., Karri, R.: Regaining trust in VLSI design: design-for-trust techniques. Proc. IEEE 102(8), 1266–1282 (2014)

    Article  Google Scholar 

  6. Alasad, Q., Bi, Y., Yuan, J.: E2LEMI: energy-efficient logic encryption using multiplexer insertion. Electronics 6, 16 (2017)

    Article  Google Scholar 

  7. Chow, L.-W., Baukus, J.P., Clark, Jr., W.M.: Integrated circuits protected against reverse engineering and method for fabricating the same using an apparent metal contact line terminating on field oxide. U.S. Patent 7,294,935, 13 November 2007

    Google Scholar 

  8. SypherMedia: Syphermedia library circuit camouflage technology. http://www.smi.tv/solutions.htm

  9. Dupuis, S., Ba, P.-S., Di Natale, G., Flottes, M.-L., Rouzeyre, B.: A novel hardware logic encryption technique for thwarting illegal overproduction and hardware trojans. In: IEEE International On-Line Testing Symposium (2014)

    Google Scholar 

  10. Rajendran, J., Pino, Y., Sinanoglu, O., Karri, R.: Logic encryption: a fault analysis perspective. In: Proceedings of the IEEE/ACM Design Automation Test in Europe, pp. 953–958 (2012)

    Google Scholar 

  11. Sree Ranjani, R., Nirmala Devi, M.: Malicious hardware detection and design for trust: an analysis. Elektrotehniski Vestnik 84(1–2), 7–16 (2017)

    Google Scholar 

  12. Chakraborty, R.S., Pagliarini, S., Mathew, J., Sree Ranjani, R., Nirmala Devi, M.: A flexible online checking technique to enhance hardware trojan horse detectability by reliability analysis. IEEE Trans. Emerg. Top. Comput. 5, 260–270 (2017)

    Article  Google Scholar 

  13. Karunakaran, D.K., Mohankumar, N.: Malicious combinational hardware Trojan detection by gate level characterization in 90 nm technology. In: 2014 International Conference on Computing, Communication and Networking Technologies (ICCCNT), pp. 1–7. IEEE (2014)

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Corresponding authors

Correspondence to Bandarupalli Chandini or M. Nirmala Devi .

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2019 Springer Nature Singapore Pte Ltd.

About this paper

Check for updates. Verify currency and authenticity via CrossMark

Cite this paper

Chandini, B., Nirmala Devi, M. (2019). Analysis of Circuits for Security Using Logic Encryption. In: Thampi, S., Madria, S., Wang, G., Rawat, D., Alcaraz Calero, J. (eds) Security in Computing and Communications. SSCC 2018. Communications in Computer and Information Science, vol 969. Springer, Singapore. https://doi.org/10.1007/978-981-13-5826-5_40

Download citation

  • DOI: https://doi.org/10.1007/978-981-13-5826-5_40

  • Published:

  • Publisher Name: Springer, Singapore

  • Print ISBN: 978-981-13-5825-8

  • Online ISBN: 978-981-13-5826-5

  • eBook Packages: Computer ScienceComputer Science (R0)

Publish with us

Policies and ethics