Abstract
The modern real time embedded applications are implemented as a mixture software-hardware designs. In the most of the hardware-software codesigns, the main processor is used to perform the part of the operation in software and to send/retrieve data to/from the hardware or co-processor. This paper proposes efficient hardware-software codesigns for AES encryptor and RS-BCH concatenated encoder, where the latency and hardware cost lie in between the fully hardware and software based designs. The synthesis results show that our proposed hardware-software codesigns of 128-bit AES and RS(255,239)-BCH(2184,2040) serial concatenated error correction encoder achieve \(85\%\) and \(40\%\) of reduction in switching power dissipation over the conventional folded AES design and [8] using Artix-7 FPGA implementation respectively.
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Mohamed Asan Basiri, M., Shukla, S.K. (2019). Efficient Hardware-Software Codesigns of AES Encryptor and RS-BCH Encoder. In: Rajaram, S., Balamurugan, N., Gracia Nirmala Rani, D., Singh, V. (eds) VLSI Design and Test. VDAT 2018. Communications in Computer and Information Science, vol 892. Springer, Singapore. https://doi.org/10.1007/978-981-13-5950-7_1
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DOI: https://doi.org/10.1007/978-981-13-5950-7_1
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