Abstract
Core of an integrated circuit is supplied test stimulus generated by an external test source and then responses of the core are compared with expected responses. Test access mechanism (TAM) is a mechanism responsible for transporting test data to the cores. Core of a three-dimensional System on Chip (SOC) has various elements related to testing of the core, known as wrapper input cells, wrapper output cells and set of scan chains. These elements are to be interconnected to form wrapper chains. To perform this, the elements are connected in an order such that the wrapper chain begins with the wrapper input cells and then internal scan chains followed by the wrapper output cells. This paper aims to determine the placement of core elements in several layers of 3D SOC for a number of wrapper chains and interconnect the core elements using available number of TSV such that the length of the longest wrapper chain is minimized.
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Kaibartta, T., Das, D.K. (2019). Optimization of Test Wrapper Length for TSV Based 3D SOCs Using a Heuristic Approach. In: Rajaram, S., Balamurugan, N., Gracia Nirmala Rani, D., Singh, V. (eds) VLSI Design and Test. VDAT 2018. Communications in Computer and Information Science, vol 892. Springer, Singapore. https://doi.org/10.1007/978-981-13-5950-7_27
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DOI: https://doi.org/10.1007/978-981-13-5950-7_27
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