Abstract
It is important to design an energy efficient underlying communication framework for multicore systems. The communication framework must satisfy the requirements of NoC (Network on Chip) such as minimum latency and minimum critical path delay. Routing on multicore framework help to compute the route to which the flit wants to reach its destination. Buffered routing consumes more power and area of the chip due to the presence of in-router buffers and buffer-less routing causes more number of deflections due to unavailability of productive port on contention. Hence, design of a minimally buffered deflection router having reduced power consumption and deflection rate is critical. There are minimally buffered deflection routers, which are characterized with minimum buffering and reduced latency. Nevertheless, limitations still exist such as higher flit latency, deflection rate. In this paper, we propose a single cycle minimally buffered deflection router with a good prioritization mechanism which leads to minimum latency and reduced deflection rate than conventional minimally buffered deflection router (MinBD). This improves the quality of NoC by prioritizing aged flits which are side buffered, redirected and re-injected in the router pipeline.
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Midhula, K.S., Babu, S., Jose, J., Jose, S. (2019). Performance Enhancement of NoCs Using Single Cycle Deflection Routers and Adaptive Priority Schemes. In: Rajaram, S., Balamurugan, N., Gracia Nirmala Rani, D., Singh, V. (eds) VLSI Design and Test. VDAT 2018. Communications in Computer and Information Science, vol 892. Springer, Singapore. https://doi.org/10.1007/978-981-13-5950-7_39
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DOI: https://doi.org/10.1007/978-981-13-5950-7_39
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