3D LBDR: Logic-Based Distributed Routing for 3D NoC

Abstract

A Network-on-Chip (NoC) is a new design in a complex system on chip (SoC) designs that provide efficient on-chip communication between networks. The design of router in NoC must be an efficient one with a lower latency and higher throughput. As the size of on-chip network grows, the distance between the cores increases in 2D NoC so the area has created the necessity to seek alternatives to the existing 2D NoCs. Exploiting the vertical dimension and migrating to 3D NoCs introduces novel structures that enable significant performance improvements over the conventional solution. So here it is the necessity of routing algorithms implementation for 3D NoCs. Using the routing table for routing in 3D NoC will increase the area of NoC because it needs memory for routing purpose. LBDR is an implementation method which is a solution of this area overhead problem. LBDR implements the routing logic without the using of routing tables at each port. LBDR enable the distributed implementation of any routing algorithm. Proposed 3D LBDR support all the algorithm which provides the minimal paths. Our proposed 3D LBDR routing implementation logic show the better handling of internal switch restriction using $R_{xx}$ bits than [6]. We are getting the throughput, average latency, and power regarding the conventional deterministic algorithm. We have also analyzed the area and power of both 2D-LBDR and 3D LBDR through hardware logic.

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