Abstract
In this paper, a survey has been made on the design of arithmetic circuits like adder, subtractor, multiplier, and squarer. There are many design schemes for those arithmetic circuits some of which have been studied and described in this paper.
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References
Landauer, R.: Irreversibility and heat generation in the computing process. IBM J. Res. Dev. 5, 183 (1961)
Castello, D.J., Forney, G.D.: Cannel coding: the road to cannel capacity. Proc. IEEE. 95(6), 1150–1177 (2007)
Bennett, C.H.: Logical reversibility of computation. IBM J. Res. Dev. 17(6), 525–532 (1973)
Berut, A., Arakelyan, A., Petrosyan, A., Ciliberto, S., Dillenschneider, R., Lutz, E.: Experimental verification of landauer/’s principle linking information and thermodynamics. Nature 483(7388), 187–189 (2012)
Hong, S., Kim, S., Papaefthymiou, M.C., Stark, W.E.: Low power parallel multiplier design for dsp applications through co-efficient optimization. In: IEEE International Conference on ASIC/SOC, pp. 286–290 (1999)
Bulic, P., Babic, Z., Avramovic, A.: A simple pipelined logarithmic multiplier. In: IEEE International Conference on Computer Design, pp. 235–240, October 2010
Mrazek, V., Sarwar, S.S., Sekanina, L., Vasicek, Z., Roy, K.: Design of power-efficient approximate multipliers for approximate artificial neural networks. In: IEEE/ACM International Conference on Computer-Aided Design, pp. 1–7 (2016)
Venkatachalam, S., Ko, S.B.: Design of power and area efficient approximate multipliers. In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 25(5), pp. 1782–1786 (2017)
Yoo, J.T., Smith, K.F., Gopalakrishnan, G.: A fast parallel squarer based on divide-and-conquer. IEEE J. Solid-State Circuits 32, 909912 (June 1997)
Deshpande, A., Draper, J.: Comparing squaring and cubing units with multipliers. In: IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 466–469 (2012)
Datla, S.R., Thornton, M.A., Matula, D.W.: A low power high performance radix-4 approximate squaring circuit. In: 20th IEEE International Conference on Application Specific Systems, Architectures and Processors (ASAP), Vol. 7, pp. 91–97 (July 2009)
Jayashree, H.V., Thapliyal, H., Agrawal, V.K.: Design of dedicated reversible quantum circuitry for square computation. In: Proceedings of 27th International Conference on VLSI Design, pp. 551–556 (January 2014)
Kotiyal, S., Thapliyal, H., Ranganathan, N.: Circuit for reversible quantum multiplier based on binary tree optimizing ancilla and garbage bits. In: Proceedings of 27th International Conferenceon VLSI Design, pp. 545–550 (January 2014)
Thapliyal, H., Ranganathan, N.: Design of efficient reversible logic based binary and bcd adder circuits. ACM J. Emerging Technol. Comput. Syst. 9(3), 17:1–17:31 (September 2013)
Thapliyal, H., Ranganathan, N., Kotiyal, S.: Design of testable reversible sequential circuits. IEEE Trans. VLSI 21(7), 1201–1209 (2013)
Thakre, A.K., Chiwande, S.S., Chafale, S.D.: Design of low power multiplier using reversible logic gate. In: Proceedings of International Conference on Green Computing Communication and Electrical Engineering (6–8 March 2014)
Madhulika, C., Nayak, V.S.P., Prasanth, C., Praveen, T.H.S.: Design of systolic array multiplier circuit using reversible logic. In: 2017 2nd IEEE International Conference on Recent Trends in Electronics, Information and Communication Technology, pp. 1670–1673 (2017)
Wille, R., Drechsler, R.: Towards a Design Flow for Reversible Logic. Springer (2010)
Peres, A.: Reversible logic and quantum computers. APS Phys. Rev. A 32, 3266–3276 (1985)
Cuccaro, S.A., Draper, T.G., Kutin, S.A.: A new quantum ripple-carry addition circuit. arXiv:quant-ph/0410184. (February 2008)
Thapliyal, H., Arabnia, H., Srinivas, M.: Efficient reversible logic design of bcd subtractors. Springer Trans. Comput. Sci. J. 3(LNCS 5300), 99–121 (2009)
Thapliyal, H., Ranganathan, N.: A new design of the reversible subtractor circuit. In: Proceedings of the 11th IEEE International Conference on Nanotechnology (IEEE NANO), pp. 1430–1435 (August 2011)
Thapliyal, H., Srinivas, M.B.: Novel reversible multiplier architecture using reversible tsg gate. In: IEEE International Conference on Computer Systems and Applications, 8th March 2006
Fredkin, E.F., Toffoli, T.: Conservative logic. Int. J. Theor. Phys. 21(3), 219–253 (1982)
Haghparast, M., Jassbi, S., Navi, K., Eshghi, M.: Optimized reversible multiplier circuits. J. Circuits Syst. Comput. 18, 311–323 (2009)
Karatsuba, A., Ofman, Y.: Multiplication of many-digital numbers by automatic computers. Doklady Akad. Nauk SSSR 145 (1963)
Offermann, S., Wille, R., Dueck, G.W., Drechsler, R.: Synthesizing multiplier in reversible logic. In: 13th IEEE Symposium on DDECS, pp. 335–340 (April 2010)
Axelsen, H.B., Thomsen, M.K.: Garbage-free integer multiplication with constants of the form \(2^{k}\pm 2^{l}\pm 1\). In: 4th Workshop on Reversible Computation (July 2012)
Saravanan, P., Chadrasekar, P., Chandran, L., Sriram, N., Kalpana, P.: Design and implementation of efficient vedic multiplier using reversible logic. In: International Symposium on VLSI Design and Test, pp. 364–366 (2012)
Banerjee, A., Das, D.K.: The design of reversible multiplier using ancient indian mathematics. In: International Symposium on Electronic Design, pp. 31–35 (December 2013)
Banerjee, A., Das, D.K.: The design of reversible signed multiplier using ancient indian mathematics. J. Low Power Electron. 11, 467–478 (December 2015)
Banerjee, A., Das, D.K.: Squaring in reversible logic using iterative structure. In: Proceedings of East West Design and Test Symposium (September 2014)
Banerjee, A., Das, D.K.: Squaring in reversible logic using zero garbage and reduced ancillary inputs. In: International Conference on VLSI Design (2015)
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Banerjee, A., Das, D.K. (2020). Arithmetic Circuits Using Reversible Logic: A Survey Report. In: Chaki, R., Cortesi, A., Saeed, K., Chaki, N. (eds) Advanced Computing and Systems for Security. Advances in Intelligent Systems and Computing, vol 995. Springer, Singapore. https://doi.org/10.1007/978-981-13-8962-7_8
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DOI: https://doi.org/10.1007/978-981-13-8962-7_8
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