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FPGA-Based Implementation of Reconfigurable Floating-Point FIR Digital Filter

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Communications, Signal Processing, and Systems (CSPS 2019)

Part of the book series: Lecture Notes in Electrical Engineering ((LNEE,volume 571))

Abstract

As a critical digital signal processing method, finite impulse response (FIR) digital filter is widely used in radar signal processing, synthetic aperture radar (SAR) signal processing, etc. Furthermore, an efficient FIR hardware implementation contributes to the practical application of these processing. However, as a computation-intensive operation, the multiple high order FIR digital filter consumes a lot of hardware resources when implemented in commonly used chips such as field-programmable gate array (FPGA). In this paper, a reconfigurable FIR digital filter architecture is presented, which can perform different order FIR filtering operation without FPGA re-programming. In the experiment, the proposed FIR digital filter architecture was implemented and validated on the Xilinx Zedboard Evaluation Kit. The experimental results demonstrate that this design has a low consumption of hardware resources and can achieve real-time processing performance for digital signal processing in the practical applications.

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Acknowledgements

This work was supported by the Chang Jiang Scholars Program under Grant T2012122 and the Hundred Leading Talent Project of Beijing Science and Technology under Grant Z141101001514005.

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Authors and Affiliations

  1. Radar Research Lab, School of Information and Electronics, Beijing Institute of Technology, Beijing, China

    Ning Zhang, Xin Wei, Bingyi Li & He Chen

  2. Beijing Key Laboratory of Embedded Real-Time Information Processing Technology, Beijing Institute of Technology, Beijing, 100081, China

    Ning Zhang, Xin Wei, Bingyi Li & He Chen

Authors
  1. Ning Zhang
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  2. Xin Wei
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  3. Bingyi Li
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  4. He Chen
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Corresponding author

Correspondence to He Chen .

Editor information

Editors and Affiliations

  1. Department of Electrical Engineering, University of Texas at Arlington, Arlington, TX, USA

    Qilian Liang

  2. College of Electronic and Communication Engineering, Tianjin Normal University, Tianjin, China

    Wei Wang

  3. School of Information and Communication Engineering, Dalian University of Technology, Dalian, Liaoning, China

    Xin Liu

  4. School of Information Science and Technology, Dalian Maritime University, Dalian, Liaoning, China

    Zhenyu Na

  5. School of Electronics and Information Engineering, Harbin Institute of Technology, Harbin, China

    Min Jia

  6. College of Physical and Electronic Information, Tianjin Normal University, Tianjin, China

    Baoju Zhang

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Zhang, N., Wei, X., Li, B., Chen, H. (2020). FPGA-Based Implementation of Reconfigurable Floating-Point FIR Digital Filter. In: Liang, Q., Wang, W., Liu, X., Na, Z., Jia, M., Zhang, B. (eds) Communications, Signal Processing, and Systems. CSPS 2019. Lecture Notes in Electrical Engineering, vol 571. Springer, Singapore. https://doi.org/10.1007/978-981-13-9409-6_47

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  • DOI: https://doi.org/10.1007/978-981-13-9409-6_47

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  • Publisher Name: Springer, Singapore

  • Print ISBN: 978-981-13-9408-9

  • Online ISBN: 978-981-13-9409-6

  • eBook Packages: EngineeringEngineering (R0)

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