Automations and Methodologies for Efficient and Quality Conscious Analog Layout Implementation

Abstract

Though there has been spectacular development of EDA tools for digital circuit implementations and validations, analog and custom circuit implementation have been slow in catching up. There are some layout design requirements unique to Analog layout such as Tiling, Fringe capacitance usage, and Dummy devices insertion for matching. Validation of Analog layout before BE delivery is another area which requires many additional checks owing to unique Analog nature such as Extended Pin, SRD, LFD, PERC, voltage marker check etc. Efforts have been put to automate some design and verifications tasks which took considerable manual effort and consumed more EDA license resources. This paper presents such automations and flow development which has resulted in productivity enhancement and ensures better quality layout deliverables. Paper presents conventional methods and practices, the proposed scripts and methodologies and gains thereof.