Abstract
This article explains an asynchronous hardware architecture for floating point multiply-accumulate circuit (MAC) that is exploited in many of the modern engineering applications such as voice/image processing, noise cancellation, and so on. The proposed asynchronous IEEE-754 single precision floating point MAC sends the previous result to the present multiplication for accumulation purpose without synchronous registers, which causes much reduction in switching power dissipations. Our proposed asynchronous design eliminates the glitches and metastability. The Wallace structure based proposed asynchronous IEEE 754 single precision floating point MAC achieves \(91.8\%\) of reduction in energy per operation (or power delay product) than base-32 based design [5] using 45 nm CMOS technology.
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Mohamed Asan Basiri, M. (2019). Asynchronous Hardware Design for Floating Point Multiply-Accumulate Circuit. In: Sengupta, A., Dasgupta, S., Singh, V., Sharma, R., Kumar Vishvakarma, S. (eds) VLSI Design and Test. VDAT 2019. Communications in Computer and Information Science, vol 1066. Springer, Singapore. https://doi.org/10.1007/978-981-32-9767-8_22
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