Abstract
A high-frequency high performance frequency synthesizer designed for 40-Gb/s SerDes is presented. In this work, a 20 GHz frequency is generated using a 10 GHz phase locked loop (PLL) that improves its power and area efficiency. The fundamental 10 GHz signal, its sufficiently strong second harmonic at 20 GHz, the divided outputs at 5/2.5/1.25 GHz are generated simultaneously using an integer-N PLL and a mixer-based frequency doubler. The proposed mixer uses an inductorless fully-differential active-inductor topology to reduce the area with marginal tradeoff in phase noise. The frequency synthesizer was designed and implemented in CMOS 55-nm technology. The doubler is integrated with a 10 GHz LC-VCO based PLL having an active area of \(390 \times 520\,\upmu \mathrm{m}^2\) (without pads), with a phase noise of −115 dBc/Hz at 10 MHz offset frequency and consumes 40.08 mW power from 1.2 V power supply, one of the lowest among the reported literature. The mixer has a maximum conversion gain (CG) of 5.46 dB, 1-dB compression point (\(P_{-1dB}\)) of −2.5 dBm and an input-referred third-order intercept point (IIP3) of −3.2 dBm. The proposed inductorless mixer-based doubler occupies an active area of \(55 \times 35\,\upmu \mathrm{m}^2\) and it adds < 1.5 dB phase noise at 20 GHz. The frequency synthesizer was used in a Serializer of the 40-Gb/s SerDes transmitter which is critical in back-haul communication for IoT and cyber physical systems.
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References
El-Nozahi, M., Sanchez-Sinencio, E., Entesari, K.: A 20–32-GHz wideband mixer with 12-GHz IF bandwidth in 0.18-\(\upmu \)m SiGe process. IEEE Trans. Microwave Theory Tech. 58(11), 2731–2740 (2010). https://doi.org/10.1109/TMTT.2010.2077572
Gaggatur, J.S., Banerjee, G.: Noise analysis in ring oscillator-based capacitance sensor interface. In: 2016 IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 1–4, October 2016. https://doi.org/10.1109/MWSCAS.2016.7870078
Gaggatur, J.S., Dixena, P.K., Banerjee, G.: A 3.2 mW 0.13\(\upmu \)m high sensitivity frequency-domain CMOS capacitance interface. In: 2016 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1070–1073, May 2016. https://doi.org/10.1109/ISCAS.2016.7527429
Gaggatur, J.S., Khatri, V., Raja, I., Lenka, M.K., Banerjee, G.: Differential multi-phase DLL for reconfigurable radio frequency synthesizer. In: 2014 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT), pp. 1–5, January 2014. https://doi.org/10.1109/CONECCT.2014.6740334
Gaggatur, J., Deshmukh, P.: A low power, high conversion gain CMOS inductorless frequency doubler for 1.25–20 GHz frequency synthesis in mm-wave receivers. In: Proceedings of the IEEE IMaRC 2018, Kolkata, India, November 2018
Li, A., Zheng, S., Yin, J., Luo, X., Luong, H.C.: A 21–48 GHz subharmonic injection-locked fractional-n frequency synthesizer for multiband point-to-point backhaul communications. IEEE J. Solid-State Circ. 49(8), 1785–1799 (2014). https://doi.org/10.1109/JSSC.2014.2320952
Monaco, E., Pozzoni, M., Svelto, F., Mazzanti, A.: Injection-locked CMOS frequency doublers for \(\mu \)-wave and mm-wave applications. IEEE J. Solid-State Circ. 45(8), 1565–1574 (2010). https://doi.org/10.1109/JSSC.2010.2049780
Musa, A., Murakami, R., Sato, T., Chiavipas, W., Okada, K., Matsuzawa, A.: A 58–63.6 GHz quadrature PLL frequency synthesizer in 65 nm CMOS. In: 2010 IEEE Asian Solid-State Circuits Conference, pp. 1–4, November 2010. https://doi.org/10.1109/ASSCC.2010.5716587
Osorio, J.F., Vaucher, C.S., Huff, B., vd Heijden, E., de Graauw, A.: A 21.7-to-27.8 GHz 2.6-degrees-rms 40mW frequency synthesizer in 45nm CMOS for mm-wave communication applications. In: 2011 IEEE International Solid-State Circuits Conference, pp. 278–280, February 2011. https://doi.org/10.1109/ISSCC.2011.5746317
Siriburanon, T., et al.: A 60-GHz sub-sampling frequency synthesizer using sub-harmonic injection-locked quadrature oscillators. In: 2014 IEEE Radio Frequency Integrated Circuits Symposium, pp. 105–108, June 2014. https://doi.org/10.1109/RFIC.2014.6851670
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The authors would like to thank the members of high speed circuits design group for the technical discussions and Terminus Circuits Pvt Ltd for the CAD tool support.
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Gaggatur, J.S., Chaturvedi, A. (2019). A 1.25–20 GHz Wide Tuning Range Frequency Synthesis for 40-Gb/s SerDes Application. In: Sengupta, A., Dasgupta, S., Singh, V., Sharma, R., Kumar Vishvakarma, S. (eds) VLSI Design and Test. VDAT 2019. Communications in Computer and Information Science, vol 1066. Springer, Singapore. https://doi.org/10.1007/978-981-32-9767-8_3
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