Abstract
The recent trend in minimizing power dissipation of digital integrated circuits through low power clock storage has motivated the design of a conditional scan pulsed latch circuit. In this paper, a power efficient two bit conditional scan pulsed latch circuit as a solution For Master Slave Flip-Flop with a conditional pulse generator circuit has been proposed for the generation of clock signal which will drive the scan latch circuit as the input clock signal. This conditional pulse generation circuit will generate a pulse signal based on the mismatch between input data and the output data at the active clock edge. With this scan pulsed latch circuit 65% power savings has been achieved when compared with traditional SCAN Master Slave Flip-Flop and 54% when compared with our own one bit conditional scan pulsed latch circuit designed using 28 nm FDSOI CMOS LVT technology.
Supported by STMicroelectronics Pvt Ltd.
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Sulthan, M., Chowdury, S.R., Garg, R., Tripathi, A. (2019). Design of a Power Efficient Pulse Latch Circuit as a Solution for Master Slave Flip-Flop. In: Sengupta, A., Dasgupta, S., Singh, V., Sharma, R., Kumar Vishvakarma, S. (eds) VLSI Design and Test. VDAT 2019. Communications in Computer and Information Science, vol 1066. Springer, Singapore. https://doi.org/10.1007/978-981-32-9767-8_44
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DOI: https://doi.org/10.1007/978-981-32-9767-8_44
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