Abstract
Advanced techniques in image processing and computer vision increasingly require that image data be represented at multiple resolutions and at multiple sample rates. Application areas for such pyramid image representations include image compression, image enhancement, motion analysis, and object recognition.
We have developed a VLSI chip, called PYR, to perform the standard filter and resampling operations required in pyramid and inverse pyramid transforms for these applications. The PYR chip processes image samples sequentially, in raster scan format, so is suited for pipeline architectures. The user can choose from a set of standard filters, through software control, to construct Gaussian, Laplacian, Subband, and related pyramid structures.
A unique feature of the design is that it includes timing signals that are passed with the image data. These signals coordinate successive processing steps in a pipeline system as image sizes and sample rates change. The chip also includes circuits for edge extension and image addition, and it can be run in “spread tap” mode to provide twice the standard sample density.
The PYR chip is implemented in standard cell technology. At a clock rate of 15 MHz, a single chip can simultaneously construct a Gaussian and a Laplacian pyramid from a 512 by 480 image in 22.7 msec (44 frame/second).
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Division of Applied Sciences Harvard University
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Van der Wal, G.S., Burt, P.J. A VLSI pyramid chip for multiresolution image analysis. Int J Comput Vision 8, 177–189 (1992). https://doi.org/10.1007/BF00055150
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DOI: https://doi.org/10.1007/BF00055150