Abstract
In this paper the testability of modified-Booth array multipliers for standard cells based design environments is examined for first time. In such cases the structure of the cells may be unknown, thus Cell Fault Model (CFM) is adopted. Two C-testable designs are proposed. A design for an N x × Ny bits modified-Booth multiplier, which uses ripple carry addition at the last stage of the multiplication, is first proposed. The design requires the addition of only one extra primary input and 38 test vectors with respect to CFM. A second C-testable design is given using carry lookahead addition at the last stage which is the case of practical implementations of modified-Booth multipliers. Such a C-testable design using carry lookahead addition is for first time proposed in the open literature. This second design requires the addition of 4 extra primary inputs. One-level and two-levels carry lookahead adders, are considered. The C-testable design requires 61 test vectors for the former and 73 test vectors for the latter, respectively. The hardware and delay overheads imposed by both C-testable designs are very small and decrease when the size of the multiplier increases.
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
References
W.H. Kautz, “Testing for Faults in Cellular Logic Arrays,” Proc. 8th Annu. Symp. Switching and Automata Theory, 1967, pp. 161–174.
A.D. Friedman, “Easily Testable Iterative Systems,” IEEE Trans. on Computers, Vol. C-22, pp. 1061–1064, Dec. 1973.
R. Parthasarathy and S.M. Reddy, “A Testable Design of Iterative Logic Arrays,” IEEE Trans. on Computers, Vol. C-30, pp. 833–841, Nov. 1981.
S.C. Seth, “Fault Diagnosis of Combinational Cellular Arrays,” Proc. 7th Annu. Conf. Circuits Syst. Theory, Oct. 1969, pp. 272–283.
P.R. Menon and A.D. Friedman, “Fault Detection in Iterative Logic Arrays,” IEEE Trans. on Computers, Vol. C-20, No. 5, pp. 524–535, May 1971.
C.H. Sung and C.L. Coates, “Tessellation Aspects of Combinational Cellular Array Testing,” IEEE Trans. on Computers, Vol. C-23, No. 4, pp. 363–368, Apr. 1974.
H. Elhuni, A. Vergis, and L. Kinney, “C-Testability of Two Dimensional Iterative Arrays,” IEEE Trans. on CAD, Vol. CAD-5, No. 4, pp. 573–581, Oct. 1986.
A. Chatterjee and J. Abraham, “Test Generation for Iterative Logic Arrays Based on an N-Cube of Cell States Model,” IEEE Trans. on Computers, Vol. C-40, No. 10, pp. 1133–1148, Oct. 1991.
J.P. Shen and F.J. Ferguson, “The Design of Easily Testable VLSI Array Multipliers,” IEEE Trans. on Computers, Vol. C-33, No. 6, pp. 554–560, June 1984.
A. Chatterjee and J.A. Abraham, “Test Generation for Arithmetic Units by Graph Labeling,” in Proc. FTCS17, July 1987, pp. 284–289.
S.J. Hong, “An Easily Testable Parallel Multiplier,” in Proc. FTCS18, June 1988, pp. 214–219.
A.R. Takach and N.K. Jha, “Easily Testable Gate Level and DCVS Multipliers,” IEEE Trans. on CAD, Vol. 10, No. 7, pp. 932–942, July 1991.
A.D. Booth, “A Signed Binary Multiplication Technique,” A. J. Mech. Appl. Math. 4, pp. 260–264, Apr. 1951.
L.P. Rubinfield, “A Proof of the Modified Booth Algorithm for Multiplication,” IEEE Trans. on Computers, Vol. C-24, pp. 1014–1015, Oct. 1975.
M. Annaratone, Digital CMOS Circuit Design, Kluwer Academic Publishers, Boston, 1986.
R. Stans, “The Testability of a Modified Booth Multiplier,” in Proc. of 1st European Test Conf, Apr. 1989, pp. 286–293.
J. van Sas, C. Nowe, D. Pollet, F. Catthoor, P. Vanoostende, and H. De Man, “Design of a C-testable Booth Multiplier Using a Realistic Fault Model,” Journal of Electronic Testing: Theory and Applications, Vol. 5, No. 1, pp. 29–41, Feb. 1994.
W.A.J. Waller and S.M. Aziz, “A C-testable Parallel Multiplier Using Differential Cascode Voltage Switch (DCVS) Logic,” IFIP Trans. A, Vol. A-42, pp. 133–142, 1994.
J. Huisken, H. Janseen, P. Lippens, O. McArdle, R. Segers, P. Zegers, A. Delaruelle, and J. van Meerberger, “Design of DSP Systems Using the Piramid Library and Design Tools,” MCNC Logic Synthesis Workshop, 1988.
H. De Man, F. Catthoor, G. Goossens, J. Vanhoof, J. van Meerbergen, and J. Huisken, “Architecture Driven Synthesis Techniques for Mapping Digital Signal Processing Algorithms into Silicon,” Proceedings of IEEE, Vol. 78, Feb. 1990, pp. 319–336.
D. Gizopoulos, D. Nikolos, A. Paschalis, and P. Kostarakis, “Ctestable Multipliers Based on the Modified Booth Algorithm,” in Proc. 3rd Asian Test Symp., Nov. 1994, pp. 163–168.
X. Huang, B. Wei, H. Chen, and Y. Mao, “High-Performance VLSI Multiplier with a New Redundant Binary Coding,” Journal of VLSI Signal Processing, Vol. 3, pp. 283–291, 1991.
VLSI Technology, Inc., “1.0 Micron CMOS VSC370 Portable Library,” Rev. 2, Apr. 1991.
D. Gizopoulos, D. Nikolos, and A. Paschalis, “Testing Combinational Iterative Logic Arrays for Realistic Faults,” in Proc. of 13th VLSI Test Symp., May 1995, pp. 35–40.
M.M. Mano, Digital Design, Prentice-Hall Inc., 1984.
H.K. Lee and D.S. Ha, “An Efficient Forward Fault Simulation Based on the Parallel Pattern Single Fault Propagation,” in Proc. of International Test Conf, Oct. 1991, pp. 946–955.
Author information
Authors and Affiliations
Rights and permissions
About this article
Cite this article
Gizopoulos, D., Nikolos, D., Paschalis, A. et al. C-Testable modified-Booth multipliers. J Electron Test 8, 241–260 (1996). https://doi.org/10.1007/BF00133387
Received:
Revised:
Issue Date:
DOI: https://doi.org/10.1007/BF00133387